From f830f790d1aa60cc8d7bad3696329aa683dc5238 Mon Sep 17 00:00:00 2001
From: Wunkolo <Wunkolo@gmail.com>
Date: Mon, 27 May 2024 13:29:19 -0700
Subject: [PATCH] [a64] Implement `OPCODE_DID_SATURATE`

This directly maps to the QC bit in the FPSR. Just have to make sure
that the saturated instruction is the very last instruction(which is
currently the case for stuff like VECTOR_ADD and such).
---
 src/xenia/cpu/backend/a64/a64_sequences.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/xenia/cpu/backend/a64/a64_sequences.cc b/src/xenia/cpu/backend/a64/a64_sequences.cc
index 94cb8fcd4..c3c0741e8 100644
--- a/src/xenia/cpu/backend/a64/a64_sequences.cc
+++ b/src/xenia/cpu/backend/a64/a64_sequences.cc
@@ -1107,8 +1107,9 @@ EMITTER_ASSOCIATIVE_COMPARE_FLT_XX(UGE, Cond::HS);  // setae
 struct DID_SATURATE
     : Sequence<DID_SATURATE, I<OPCODE_DID_SATURATE, I8Op, V128Op>> {
   static void Emit(A64Emitter& e, const EmitArgType& i) {
-    // TODO(benvanik): implement saturation check (VECTOR_ADD, etc).
-    e.EOR(i.dest, i.dest, i.dest);
+    // Bit 27 in the FPSR is the QC bit
+    e.MRS(X0, SystemReg::FPSR);
+    e.UBFX(i.dest, W0, 27, 1);
   }
 };
 EMITTER_OPCODE_TABLE(OPCODE_DID_SATURATE, DID_SATURATE);