vctsxs tests.

src/alloy/frontend/ppc/test/bin/instr_vctsxs.dis

@@ -0,0 +1,25 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vctsxs.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vctsxs_1>:
+  100000:	10 60 1b ca 	vctsxs  v3,v3,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vctsxs_2>:
+  100008:	10 61 1b ca 	vctsxs  v3,v3,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vctsxs_3>:
+  100010:	10 62 1b ca 	vctsxs  v3,v3,2
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vctsxs_4>:
+  100018:	10 60 1b ca 	vctsxs  v3,v3,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vctsxs_5>:
+  100020:	10 61 1b ca 	vctsxs  v3,v3,1
+  100024:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vctsxs.map

@@ -0,0 +1,5 @@
+0000000000000000 t test_vctsxs_1
+0000000000000008 t test_vctsxs_2
+0000000000000010 t test_vctsxs_3
+0000000000000018 t test_vctsxs_4
+0000000000000020 t test_vctsxs_5

src/alloy/frontend/ppc/test/instr_vctsxs.s

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+test_vctsxs_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+
+test_vctsxs_2:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 1
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000003, 00000002, 00000003]
+
+test_vctsxs_3:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9
+  vctsxs v3, v3, 2
+  blr
+  #_ REGISTER_OUT v3 [00000004, 00000006, 00000004, 00000007]
+
+test_vctsxs_4:
+  #_ REGISTER_IN v3 [42c83333, 43480000, 449a4000, c49a4000]
+  vctsxs v3, v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000064, 000000c8, 000004d2, fffffb2e]
+
+test_vctsxs_5:
+  #_ REGISTER_IN v3 [42c83333, 43480000, 449a4000, c49a4000]
+  vctsxs v3, v3, 1
+  blr
+  #_ REGISTER_OUT v3 [000000c8, 00000190, 000009a4, fffff65c]