srdi special case and tests for sldi/srdi.

src/alloy/frontend/ppc/ppc_emit_alu.cc

@@ -837,11 +837,16 @@ XEEMITTER(rld, 0x78000000, MDS)(PPCHIRBuilder& f, InstrData& i) {
     uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
     uint64_t m = XEMASK(mb, 63);
     Value* v = f.LoadGPR(i.MD.RT);
-    if (sh) {
-      v = f.RotateLeft(v, f.LoadConstant((int8_t)sh));
-    }
-    if (m != 0xFFFFFFFFFFFFFFFF) {
-      v = f.And(v, f.LoadConstant(m));
+    if (sh == 64 - mb) {
+      // srdi == rldicl ra,rs,64-n,n
+      v = f.Shr(v, int8_t(mb));
+    } else {
+      if (sh) {
+        v = f.RotateLeft(v, f.LoadConstant((int8_t)sh));
+      }
+      if (m != 0xFFFFFFFFFFFFFFFF) {
+        v = f.And(v, f.LoadConstant(m));
+      }
     }
     f.StoreGPR(i.MD.RA, v);
     if (i.MD.Rc) {
@@ -860,8 +865,8 @@ XEEMITTER(rld, 0x78000000, MDS)(PPCHIRBuilder& f, InstrData& i) {
     uint64_t m = XEMASK(0, mb);
     Value* v = f.LoadGPR(i.MD.RT);
     if (mb == 63 - sh) {
-      // Shift left.
-      v = f.Shl(v, f.LoadConstant((int8_t)sh));
+      // sldi ==  rldicr ra,rs,n,63-n
+      v = f.Shl(v, int8_t(sh));
     } else {
       if (sh) {
         v = f.RotateLeft(v, f.LoadConstant((int8_t)sh));

src/alloy/frontend/ppc/test/bin/instr_rldicl.dis

@@ -43,3 +43,23 @@ Disassembly of section .text:
 0000000000100048 <test_rldicl_10>:
   100048:	78 83 d1 82 	rldicl  r3,r4,58,6
   10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_srdi_1>:
+  100050:	78 63 00 00 	rotldi  r3,r3,0
+  100054:	78 84 00 00 	rotldi  r4,r4,0
+  100058:	4e 80 00 20 	blr
+
+000000000010005c <test_srdi_2>:
+  10005c:	78 63 f8 42 	rldicl  r3,r3,63,1
+  100060:	78 84 f8 42 	rldicl  r4,r4,63,1
+  100064:	4e 80 00 20 	blr
+
+0000000000100068 <test_srdi_3>:
+  100068:	78 63 00 22 	rldicl  r3,r3,32,32
+  10006c:	78 84 00 22 	rldicl  r4,r4,32,32
+  100070:	4e 80 00 20 	blr
+
+0000000000100074 <test_srdi_4>:
+  100074:	78 63 0f e0 	rldicl  r3,r3,1,63
+  100078:	78 84 0f e0 	rldicl  r4,r4,1,63
+  10007c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rldicl.map

@@ -8,3 +8,7 @@
 0000000000000038 t test_rldicl_8
 0000000000000040 t test_rldicl_9
 0000000000000048 t test_rldicl_10
+0000000000000050 t test_srdi_1
+000000000000005c t test_srdi_2
+0000000000000068 t test_srdi_3
+0000000000000074 t test_srdi_4

src/alloy/frontend/ppc/test/bin/instr_rldicr.dis

@@ -39,3 +39,23 @@ Disassembly of section .text:
 0000000000100040 <test_rldicr_9>:
   100040:	78 83 f8 04 	rldicr  r3,r4,31,0
   100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_sldi_1>:
+  100048:	78 63 07 e4 	rldicr  r3,r3,0,63
+  10004c:	78 84 07 e4 	rldicr  r4,r4,0,63
+  100050:	4e 80 00 20 	blr
+
+0000000000100054 <test_sldi_2>:
+  100054:	78 63 0f a4 	rldicr  r3,r3,1,62
+  100058:	78 84 0f a4 	rldicr  r4,r4,1,62
+  10005c:	4e 80 00 20 	blr
+
+0000000000100060 <test_sldi_3>:
+  100060:	78 63 07 c6 	rldicr  r3,r3,32,31
+  100064:	78 84 07 c6 	rldicr  r4,r4,32,31
+  100068:	4e 80 00 20 	blr
+
+000000000010006c <test_sldi_4>:
+  10006c:	78 63 f8 06 	rldicr  r3,r3,63,0
+  100070:	78 84 f8 06 	rldicr  r4,r4,63,0
+  100074:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rldicr.map

@@ -7,3 +7,7 @@
 0000000000000030 t test_rldicr_7
 0000000000000038 t test_rldicr_8
 0000000000000040 t test_rldicr_9
+0000000000000048 t test_sldi_1
+0000000000000054 t test_sldi_2
+0000000000000060 t test_sldi_3
+000000000000006c t test_sldi_4

src/alloy/frontend/ppc/test/instr_rldicl.s

@@ -67,3 +67,39 @@ test_rldicl_10:
   blr
   #_ REGISTER_OUT r3 0x58C000
   #_ REGISTER_OUT r4 0x16300000
+
+test_srdi_1:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 0
+  srdi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_srdi_2:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 1
+  srdi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0x7fffffffffffffff
+  #_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
+
+test_srdi_3:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 32
+  srdi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0x00000000ffffffff
+  #_ REGISTER_OUT r4 0x0000000001234567
+
+test_srdi_4:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  srdi r3, r3, 63
+  srdi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000000

src/alloy/frontend/ppc/test/instr_rldicr.s

@@ -60,3 +60,39 @@ test_rldicr_9:
   blr
   #_ REGISTER_OUT r3 0x8000000000000000
   #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_sldi_1:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 0
+  sldi r4, r4, 0
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x0123456789ABCDEF
+
+test_sldi_2:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 1
+  sldi r4, r4, 1
+  blr
+  #_ REGISTER_OUT r3 0xfffffffffffffffe
+  #_ REGISTER_OUT r4 0x02468acf13579bde
+
+test_sldi_3:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 32
+  sldi r4, r4, 32
+  blr
+  #_ REGISTER_OUT r3 0xffffffff00000000
+  #_ REGISTER_OUT r4 0x89abcdef00000000
+
+test_sldi_4:
+  #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r4 0x0123456789ABCDEF
+  sldi r3, r3, 63
+  sldi r4, r4, 63
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r4 0x8000000000000000