diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.bin b/src/alloy/frontend/ppc/test/bin/instr_vrfin.bin
new file mode 100644
index 000000000..c236bb45d
Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vrfin.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.dis b/src/alloy/frontend/ppc/test/bin/instr_vrfin.dis
new file mode 100644
index 000000000..3d7f0a2cd
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vrfin.dis
@@ -0,0 +1,13 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vrfin.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vrfin_1>:
+  100000:	10 60 1a 0a 	vrfin   v3,v3
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vrfin_2>:
+  100008:	10 60 1a 0a 	vrfin   v3,v3
+  10000c:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrfin.map b/src/alloy/frontend/ppc/test/bin/instr_vrfin.map
new file mode 100644
index 000000000..42705011b
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vrfin.map
@@ -0,0 +1,2 @@
+0000000000000000 t test_vrfin_1
+0000000000000008 t test_vrfin_2
diff --git a/src/alloy/frontend/ppc/test/instr_vrfin.s b/src/alloy/frontend/ppc/test/instr_vrfin.s
new file mode 100644
index 000000000..cf31be55e
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_vrfin.s
@@ -0,0 +1,13 @@
+test_vrfin_1:
+  #_ REGISTER_IN v3 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
+  # 1.0, 1.5, 1.1, 1.9 -> 1.0, 2.0, 1.0, 2.0
+  vrfin v3, v3
+  blr
+  #_ REGISTER_OUT v3 [3f800000, 40000000, 3f800000, 40000000]
+
+test_vrfin_2:
+  #_ REGISTER_IN v3 [bf800000, bfc00000, bf8ccccd, bff33333]
+  # -1.0, -1.5, -1.1, -1.9 -> -1.0, -2.0, -1.0, -2.0
+  vrfin v3, v3
+  blr
+  #_ REGISTER_OUT v3 [bf800000, c0000000, bf800000, c0000000]