From ef3bd6cc53e8d88eee73acf6e5d282fd53f54391 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Fri, 24 May 2013 23:03:35 -0700
Subject: [PATCH] Fixing disasm of subfic, fixing neg->not, fixing tests to use
 8bits.

---
 src/xenia/cpu/ppc/disasm_alu.cc       |  6 +++---
 src/xenia/cpu/x64/x64_emit_alu.cc     | 10 +++++-----
 src/xenia/cpu/x64/x64_emit_control.cc |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/xenia/cpu/ppc/disasm_alu.cc b/src/xenia/cpu/ppc/disasm_alu.cc
index 861b1c4d3..66b3c2bc6 100644
--- a/src/xenia/cpu/ppc/disasm_alu.cc
+++ b/src/xenia/cpu/ppc/disasm_alu.cc
@@ -232,9 +232,9 @@ XEDISASMR(subfcx,       0x7C000010, XO )(InstrData& i, InstrDisasm& d) {
 
 XEDISASMR(subficx,      0x20000000, D  )(InstrData& i, InstrDisasm& d) {
   d.Init("subfic", "Subtract From Immediate Carrying", InstrDisasm::kCA);
-  d.AddRegOperand(InstrRegister::kGPR, i.XO.RT, InstrRegister::kWrite);
-  d.AddRegOperand(InstrRegister::kGPR, i.XO.RA, InstrRegister::kRead);
-  d.AddRegOperand(InstrRegister::kGPR, i.XO.RB, InstrRegister::kRead);
+  d.AddRegOperand(InstrRegister::kGPR, i.D.RT, InstrRegister::kWrite);
+  d.AddRegOperand(InstrRegister::kGPR, i.D.RA, InstrRegister::kRead);
+  d.AddSImmOperand(XEEXTS16(i.D.DS), 2);
   return d.Finish();
 }
 
diff --git a/src/xenia/cpu/x64/x64_emit_alu.cc b/src/xenia/cpu/x64/x64_emit_alu.cc
index 099c5ef4e..3cab4f05d 100644
--- a/src/xenia/cpu/x64/x64_emit_alu.cc
+++ b/src/xenia/cpu/x64/x64_emit_alu.cc
@@ -378,7 +378,7 @@ XEEMITTER(subfx,        0x7C000050, XO )(X64Emitter& e, X86Compiler& c, InstrDat
 
   GpVar v(c.newGpVar());
   c.mov(v, e.gpr_value(i.XO.RA));
-  c.neg(v);
+  c.not_(v);
   c.stc();  // Always carrying.
   c.adc(v, e.gpr_value(i.XO.RB));
 
@@ -408,7 +408,7 @@ XEEMITTER(subficx,      0x20000000, D  )(X64Emitter& e, X86Compiler& c, InstrDat
 
   GpVar v(c.newGpVar());
   c.mov(v, e.gpr_value(i.D.RA));
-  c.neg(v);
+  c.not_(v);
   c.stc();  // Always carrying.
   c.adc(v, imm(XEEXTS16(i.D.DS)));
   GpVar cc(c.newGpVar());
@@ -425,7 +425,7 @@ XEEMITTER(subfex,       0x7C000110, XO )(X64Emitter& e, X86Compiler& c, InstrDat
 
   GpVar v(c.newGpVar());
   c.mov(v, e.gpr_value(i.XO.RA));
-  c.neg(v);
+  c.not_(v);
 
   // Add in carry flag from XER, only if needed.
   // It may be possible to do this much more efficiently.
@@ -619,7 +619,7 @@ XEEMITTER(andcx,        0x7C000078, X  )(X64Emitter& e, X86Compiler& c, InstrDat
 
   GpVar v(c.newGpVar());
   c.mov(v, e.gpr_value(i.X.RB));
-  c.neg(v);
+  c.not_(v);
   c.and_(v, e.gpr_value(i.X.RT));
   e.update_gpr_value(i.X.RA, v);
 
@@ -740,7 +740,7 @@ XEEMITTER(norx,         0x7C0000F8, X  )(X64Emitter& e, X86Compiler& c, InstrDat
   GpVar v(c.newGpVar());
   c.mov(v, e.gpr_value(i.X.RT));
   c.or_(v, e.gpr_value(i.X.RB));
-  c.neg(v);
+  c.not_(v);
   e.update_gpr_value(i.X.RA, v);
 
   if (i.X.Rc) {
diff --git a/src/xenia/cpu/x64/x64_emit_control.cc b/src/xenia/cpu/x64/x64_emit_control.cc
index 761ace06c..46e378c59 100644
--- a/src/xenia/cpu/x64/x64_emit_control.cc
+++ b/src/xenia/cpu/x64/x64_emit_control.cc
@@ -80,7 +80,7 @@ int XeEmitBranchTo(
     if (condition) {
       // Fast test -- if condition passed then jump to target.
       // TODO(benvanik): need to spill here? somehow?
-      c.test(*condition, *condition);
+      c.test((*condition).r8(), (*condition).r8());
       c.jnz(target_label);
     } else {
       // TODO(benvanik): need to spill here?
@@ -95,7 +95,7 @@ int XeEmitBranchTo(
   if (condition) {
     // TODO(benvanik): add debug info for this?
     post_jump_label = c.newLabel();
-    c.test(*condition, *condition);
+    c.test((*condition).r8(), (*condition).r8());
     // TODO(benvanik): experiment with various hints?
     c.jz(post_jump_label, kCondHintNone);
   }