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[GPU] Move gamma ramp tracking to CommandProcessor.

This commit is contained in:
gibbed 2018-05-22 05:36:24 -05:00
parent fb650ae024
commit ee5724f5dd
4 changed files with 85 additions and 85 deletions
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35
src/xenia/gpu/command_processor.cc
View File

@ -288,6 +288,41 @@ void CommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
}
}
void CommandProcessor::UpdateGammaRampValue(GammaRampType type,
uint32_t value) {
RegisterFile* regs = register_file_;
auto index = regs->values[XE_GPU_REG_DC_LUT_RW_INDEX].u32;
auto mask = regs->values[XE_GPU_REG_DC_LUT_WRITE_EN_MASK].u32;
auto mask_lo = (mask >> 0) & 0x7;
auto mask_hi = (mask >> 3) & 0x7;
// If games update individual components we're going to have a problem.
assert_true(mask_lo == 0 || mask_lo == 7);
assert_true(mask_hi == 0);
auto subindex = gamma_ramp_rw_subindex_;
if (mask_lo) {
switch (type) {
case GammaRampType::kNormal:
assert_true(regs->values[XE_GPU_REG_DC_LUT_RW_MODE].u32 == 0);
gamma_ramp_.normal[index].value = value;
break;
case GammaRampType::kPWL:
assert_true(regs->values[XE_GPU_REG_DC_LUT_RW_MODE].u32 == 1);
gamma_ramp_.pwl[index].values[subindex].value = value;
break;
default:
assert_unhandled_case(type);
}
}
gamma_ramp_rw_subindex_ = (subindex + 1) % 3;
dirty_gamma_ramp_ = true;
}
void CommandProcessor::MakeCoherent() {
SCOPE_profile_cpu_f("gpu");

50
src/xenia/gpu/command_processor.h
View File

@ -58,6 +58,50 @@ enum class SwapMode {
kIgnored,
};
enum class GammaRampType {
kUnknown = 0,
kNormal,
kPWL,
};
struct GammaRamp {
struct NormalEntry {
union {
struct {
uint32_t r : 10;
uint32_t g : 10;
uint32_t b : 10;
uint32_t : 2;
};
uint32_t value;
};
};
struct PWLValue {
union {
struct {
uint16_t base;
uint16_t delta;
};
uint32_t value;
};
};
struct PWLEntry {
union {
struct {
PWLValue r;
PWLValue g;
PWLValue b;
};
PWLValue values[3];
};
};
NormalEntry normal[256];
PWLEntry pwl[256];
};
class CommandProcessor {
public:
CommandProcessor(GraphicsSystem* graphics_system,
@ -119,6 +163,8 @@ class CommandProcessor {
virtual void WriteRegister(uint32_t index, uint32_t value);
void UpdateGammaRampValue(GammaRampType type, uint32_t value);
virtual void MakeCoherent();
virtual void PrepareForWait();
virtual void ReturnFromWait();
@ -237,6 +283,10 @@ class CommandProcessor {
Shader* active_pixel_shader_ = nullptr;
bool paused_ = false;
GammaRamp gamma_ramp_ = {};
int gamma_ramp_rw_subindex_ = 0;
bool dirty_gamma_ramp_ = true;
};
} // namespace gpu

35
src/xenia/gpu/vulkan/vulkan_command_processor.cc
View File

@ -229,41 +229,6 @@ void VulkanCommandProcessor::WriteRegister(uint32_t index, uint32_t value) {
}
}
void VulkanCommandProcessor::UpdateGammaRampValue(GammaRampType type,
uint32_t value) {
RegisterFile* regs = register_file_;
auto index = regs->values[XE_GPU_REG_DC_LUT_RW_INDEX].u32;
auto mask = regs->values[XE_GPU_REG_DC_LUT_WRITE_EN_MASK].u32;
auto mask_lo = (mask >> 0) & 0x7;
auto mask_hi = (mask >> 3) & 0x7;
// If games update individual components we're going to have a problem.
assert_true(mask_lo == 0 || mask_lo == 7);
assert_true(mask_hi == 0);
auto subindex = gamma_ramp_rw_subindex_;
if (mask_lo) {
switch (type) {
case GammaRampType::kNormal:
assert_true(regs->values[XE_GPU_REG_DC_LUT_RW_MODE].u32 == 0);
gamma_ramp_.normal[index].value = value;
break;
case GammaRampType::kPWL:
assert_true(regs->values[XE_GPU_REG_DC_LUT_RW_MODE].u32 == 1);
gamma_ramp_.pwl[index].values[subindex].value = value;
break;
default:
assert_unhandled_case(type);
}
}
gamma_ramp_rw_subindex_ = (subindex + 1) % 3;
dirty_gamma_ramp_ = true;
}
void VulkanCommandProcessor::CreateSwapImage(VkCommandBuffer setup_buffer,
VkExtent2D extents) {
VkImageCreateInfo image_info;

50
src/xenia/gpu/vulkan/vulkan_command_processor.h
View File

@ -44,50 +44,6 @@ namespace vulkan {
class VulkanGraphicsSystem;
class TextureCache;
enum class GammaRampType {
kUnknown = 0,
kNormal,
kPWL,
};
struct GammaRamp {
struct NormalEntry {
union {
struct {
uint32_t r : 10;
uint32_t g : 10;
uint32_t b : 10;
uint32_t : 2;
};
uint32_t value;
};
};
struct PWLValue {
union {
struct {
uint16_t base;
uint16_t delta;
};
uint32_t value;
};
};
struct PWLEntry {
union {
struct {
PWLValue r;
PWLValue g;
PWLValue b;
};
PWLValue values[3];
};
};
NormalEntry normal[256];
PWLEntry pwl[256];
};
class VulkanCommandProcessor : public CommandProcessor {
public:
VulkanCommandProcessor(VulkanGraphicsSystem* graphics_system,
@ -138,8 +94,6 @@ class VulkanCommandProcessor : public CommandProcessor {
VulkanShader* pixel_shader);
bool IssueCopy() override;
void UpdateGammaRampValue(GammaRampType type, uint32_t value);
xe::ui::vulkan::VulkanDevice* device_ = nullptr;
// front buffer / back buffer memory
@ -183,10 +137,6 @@ class VulkanCommandProcessor : public CommandProcessor {
VkCommandBuffer current_command_buffer_ = nullptr;
VkCommandBuffer current_setup_buffer_ = nullptr;
VkFence current_batch_fence_;
GammaRamp gamma_ramp_ = {};
int gamma_ramp_rw_subindex_ = 0;
bool dirty_gamma_ramp_ = true;
};
} // namespace vulkan