diff --git a/src/xenia/gpu/d3d12/pipeline_cache.cc b/src/xenia/gpu/d3d12/pipeline_cache.cc
index f67312436..3243a285a 100644
--- a/src/xenia/gpu/d3d12/pipeline_cache.cc
+++ b/src/xenia/gpu/d3d12/pipeline_cache.cc
@@ -686,6 +686,16 @@ PipelineCache::Pipeline* PipelineCache::GetPipeline(uint64_t hash_key) {
 
   // TODO(Triang3l): Cache create pipelines using CachedPSO.
 
+  if (update_shader_stages_regs_.pixel_shader != nullptr) {
+    XELOGGPU(
+        "Creating pipeline %.16" PRIX64 ", VS %.16" PRIX64 ", PS %.16" PRIX64,
+        hash_key, update_shader_stages_regs_.vertex_shader->ucode_data_hash(),
+        update_shader_stages_regs_.pixel_shader->ucode_data_hash());
+  } else {
+    XELOGGPU("Creating pipeline %.16" PRIX64 ", VS %.16" PRIX64, hash_key,
+             update_shader_stages_regs_.vertex_shader->ucode_data_hash());
+  }
+
   auto device =
       command_processor_->GetD3D12Context()->GetD3D12Provider()->GetDevice();
   ID3D12PipelineState* state;
diff --git a/src/xenia/gpu/d3d12/texture_cache.cc b/src/xenia/gpu/d3d12/texture_cache.cc
index 75ba0f379..1edf02b10 100644
--- a/src/xenia/gpu/d3d12/texture_cache.cc
+++ b/src/xenia/gpu/d3d12/texture_cache.cc
@@ -1111,8 +1111,8 @@ void TextureCache::WatchCallback(Texture* texture, bool is_mip) {
     texture->base_in_sync = false;
     texture->base_watch_handle = nullptr;
   }
-  XELOGE("Texture %s at %.8X invalidated", is_mip ? "mips" : "base",
-         (is_mip ? texture->key.mip_page : texture->key.base_page) << 12);
+  XELOGGPU("Texture %s at 0x%.8X invalidated", is_mip ? "mips" : "base",
+           (is_mip ? texture->key.mip_page : texture->key.base_page) << 12);
   texture_invalidated_.store(true, std::memory_order_relaxed);
 }