From e7b03042bacc781b2ee769b65783692ac376bb16 Mon Sep 17 00:00:00 2001 From: gibbed Date: Wed, 13 May 2015 01:01:00 -0500 Subject: [PATCH] Constant tests for addic, addme, addze, divd, divdu. --- src/xenia/cpu/frontend/test/instr_addic.s | 18 +++++ src/xenia/cpu/frontend/test/instr_addme.s | 84 +++++++++++++++++++++++ src/xenia/cpu/frontend/test/instr_addze.s | 84 +++++++++++++++++++++++ src/xenia/cpu/frontend/test/instr_divd.s | 84 +++++++++++++++++++++++ src/xenia/cpu/frontend/test/instr_divdu.s | 84 +++++++++++++++++++++++ 5 files changed, 354 insertions(+) diff --git a/src/xenia/cpu/frontend/test/instr_addic.s b/src/xenia/cpu/frontend/test/instr_addic.s index 13b96d6f7..9a64d1a2c 100644 --- a/src/xenia/cpu/frontend/test/instr_addic.s +++ b/src/xenia/cpu/frontend/test/instr_addic.s @@ -1,3 +1,5 @@ +# constant tests are commented since add_carry isn't supported + test_addic_1: #_ REGISTER_IN r4 1 addic r4, r4, 1 @@ -6,6 +8,14 @@ test_addic_1: #_ REGISTER_OUT r4 2 #_ REGISTER_OUT r6 0 +#test_addic_1_constant: +# li r4, 1 +# addic r4, r4, 1 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r4 2 +# #_ REGISTER_OUT r6 0 + test_addic_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF addic r4, r4, 1 @@ -13,3 +23,11 @@ test_addic_2: blr #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r6 1 + +#test_addic_2_constant: +# li r4, -1 +# addic r4, r4, 1 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r4 0 +# #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_addme.s b/src/xenia/cpu/frontend/test/instr_addme.s index afea951b3..2dc15b58d 100644 --- a/src/xenia/cpu/frontend/test/instr_addme.s +++ b/src/xenia/cpu/frontend/test/instr_addme.s @@ -7,6 +7,15 @@ test_addme_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 1 +test_addme_1_constant: + li r4, 1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 1 + test_addme_2: #_ REGISTER_IN r4 1 xor r3, r3, r3 @@ -19,6 +28,18 @@ test_addme_2: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 1 +test_addme_2_constant: + li r4, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 1 + test_addme_3: #_ REGISTER_IN r4 12 addme r3, r4 @@ -28,6 +49,15 @@ test_addme_3: #_ REGISTER_OUT r4 12 #_ REGISTER_OUT r6 1 +test_addme_3_constant: + li r4, 12 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 11 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 1 + test_addme_4: #_ REGISTER_IN r4 12 xor r3, r3, r3 @@ -40,6 +70,18 @@ test_addme_4: #_ REGISTER_OUT r4 12 #_ REGISTER_OUT r6 1 +test_addme_4_constant: + li r4, 12 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 12 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 1 + test_addme_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF addme r3, r4 @@ -49,6 +91,15 @@ test_addme_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_addme_5_constant: + li r4, -1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_addme_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -61,6 +112,18 @@ test_addme_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_addme_6_constant: + li r4, -1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_addme_7: #_ REGISTER_IN r4 0 addme r3, r4 @@ -70,6 +133,15 @@ test_addme_7: #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r6 0 +test_addme_7_constant: + li r4, 0 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0 + test_addme_8: #_ REGISTER_IN r4 0 xor r3, r3, r3 @@ -81,3 +153,15 @@ test_addme_8: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r6 1 + +test_addme_8_constant: + li r4, 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_addze.s b/src/xenia/cpu/frontend/test/instr_addze.s index 17c4942b9..d35efaa70 100644 --- a/src/xenia/cpu/frontend/test/instr_addze.s +++ b/src/xenia/cpu/frontend/test/instr_addze.s @@ -7,6 +7,15 @@ test_addze_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 0 +test_addze_1_constant: + li r4, 1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + test_addze_2: #_ REGISTER_IN r4 1 xor r3, r3, r3 @@ -19,6 +28,18 @@ test_addze_2: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 0 +test_addze_2_constant: + li r4, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 2 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + test_addze_3: #_ REGISTER_IN r4 12 addze r3, r4 @@ -28,6 +49,15 @@ test_addze_3: #_ REGISTER_OUT r4 12 #_ REGISTER_OUT r6 0 +test_addze_3_constant: + li r4, 12 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 12 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 0 + test_addze_4: #_ REGISTER_IN r4 12 xor r3, r3, r3 @@ -40,6 +70,18 @@ test_addze_4: #_ REGISTER_OUT r4 12 #_ REGISTER_OUT r6 0 +test_addze_4_constant: + li r4, 12 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 13 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 0 + test_addze_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF addze r3, r4 @@ -49,6 +91,15 @@ test_addze_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 0 +test_addze_5_constant: + li r4, -1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + test_addze_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -61,6 +112,18 @@ test_addze_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_addze_6_constant: + li r4, -1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_addze_7: #_ REGISTER_IN r4 0 addze r3, r4 @@ -70,6 +133,15 @@ test_addze_7: #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r6 0 +test_addze_7_constant: + li r4, 0 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0 + test_addze_8: #_ REGISTER_IN r4 0 xor r3, r3, r3 @@ -81,3 +153,15 @@ test_addze_8: #_ REGISTER_OUT r3 1 #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r6 0 + +test_addze_8_constant: + li r4, 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0 diff --git a/src/xenia/cpu/frontend/test/instr_divd.s b/src/xenia/cpu/frontend/test/instr_divd.s index 35928c66c..cafc90a69 100644 --- a/src/xenia/cpu/frontend/test/instr_divd.s +++ b/src/xenia/cpu/frontend/test/instr_divd.s @@ -7,6 +7,15 @@ test_divd_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 2 +test_divd_1_constant: + li r4, 1 + li r5, 2 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + # TODO(benvanik): x64 ignore divide by zero (=0) #test_divd_2: # #_ REGISTER_IN r4 1 @@ -17,6 +26,16 @@ test_divd_1: # #_ REGISTER_OUT r4 1 # #_ REGISTER_OUT r5 0 +# TODO(benvanik): x64 ignore divide by zero (=0) +#test_divd_2_constant: +# li r4, 1 +# li r5, 0 +# divd r3, r4, r5 +# blr +# #_ REGISTER_OUT r3 0 +# #_ REGISTER_OUT r4 1 +# #_ REGISTER_OUT r5 0 + test_divd_3: #_ REGISTER_IN r4 2 #_ REGISTER_IN r5 1 @@ -26,6 +45,15 @@ test_divd_3: #_ REGISTER_OUT r4 2 #_ REGISTER_OUT r5 1 +test_divd_3_constant: + li r4, 2 + li r5, 1 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 2 + #_ REGISTER_OUT r4 2 + #_ REGISTER_OUT r5 1 + test_divd_4: #_ REGISTER_IN r4 35 #_ REGISTER_IN r5 7 @@ -35,6 +63,15 @@ test_divd_4: #_ REGISTER_OUT r4 35 #_ REGISTER_OUT r5 7 +test_divd_4_constant: + li r4, 35 + li r5, 7 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 5 + #_ REGISTER_OUT r4 35 + #_ REGISTER_OUT r5 7 + test_divd_5: #_ REGISTER_IN r4 0 #_ REGISTER_IN r5 1 @@ -44,6 +81,15 @@ test_divd_5: #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r5 1 +test_divd_5_constant: + li r4, 0 + li r5, 1 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 1 + test_divd_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -53,6 +99,15 @@ test_divd_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_divd_6_constant: + li r4, -1 + li r5, 1 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_divd_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -62,6 +117,15 @@ test_divd_7: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF +test_divd_7_constant: + li r4, -1 + li r5, -1 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + test_divd_8: #_ REGISTER_IN r4 1 #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -71,6 +135,15 @@ test_divd_8: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF +test_divd_8_constant: + li r4, 1 + li r5, -1 + divd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + # TODO(benvanik): integer overflow (=0) #test_divd_9: # #_ REGISTER_IN r4 0x8000000000000000 @@ -80,3 +153,14 @@ test_divd_8: # #_ REGISTER_OUT r3 0 # #_ REGISTER_OUT r4 0x8000000000000000 # #_ REGISTER_OUT r5 -1 + +# TODO(benvanik): integer overflow (=0) +#test_divd_9_constant: +# li r4, 1 +# sldi r4, r4, 63 +# li r5, -1 +# divd r3, r4, r5 +# blr +# #_ REGISTER_OUT r3 0 +# #_ REGISTER_OUT r4 0x8000000000000000 +# #_ REGISTER_OUT r5 -1 diff --git a/src/xenia/cpu/frontend/test/instr_divdu.s b/src/xenia/cpu/frontend/test/instr_divdu.s index f69d1bfec..cd073859c 100644 --- a/src/xenia/cpu/frontend/test/instr_divdu.s +++ b/src/xenia/cpu/frontend/test/instr_divdu.s @@ -7,6 +7,15 @@ test_divdu_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 2 +test_divdu_1_constant: + li r4, 1 + li r5, 2 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + # TODO(benvanik): x64 ignore divide by zero (=0) #test_divdu_2: # #_ REGISTER_IN r4 1 @@ -17,6 +26,16 @@ test_divdu_1: # #_ REGISTER_OUT r4 1 # #_ REGISTER_OUT r5 0 +# TODO(benvanik): x64 ignore divide by zero (=0) +#test_divdu_2_constant: +# li r4, 1 +# li r5, 0 +# divdu r3, r4, r5 +# blr +# #_ REGISTER_OUT r3 0 +# #_ REGISTER_OUT r4 1 +# #_ REGISTER_OUT r5 0 + test_divdu_3: #_ REGISTER_IN r4 2 #_ REGISTER_IN r5 1 @@ -26,6 +45,15 @@ test_divdu_3: #_ REGISTER_OUT r4 2 #_ REGISTER_OUT r5 1 +test_divdu_3_constant: + li r4, 2 + li r5, 1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 2 + #_ REGISTER_OUT r4 2 + #_ REGISTER_OUT r5 1 + test_divdu_4: #_ REGISTER_IN r4 35 #_ REGISTER_IN r5 7 @@ -35,6 +63,15 @@ test_divdu_4: #_ REGISTER_OUT r4 35 #_ REGISTER_OUT r5 7 +test_divdu_4_constant: + li r4, 35 + li r5, 7 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 5 + #_ REGISTER_OUT r4 35 + #_ REGISTER_OUT r5 7 + test_divdu_5: #_ REGISTER_IN r4 0 #_ REGISTER_IN r5 1 @@ -44,6 +81,15 @@ test_divdu_5: #_ REGISTER_OUT r4 0 #_ REGISTER_OUT r5 1 +test_divdu_5_constant: + li r4, 0 + li r5, 1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r5 1 + test_divdu_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -53,6 +99,15 @@ test_divdu_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_divdu_6_constant: + li r4, -1 + li r5, 1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_divdu_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -62,6 +117,15 @@ test_divdu_7: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF +test_divdu_7_constant: + li r4, -1 + li r5, -1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + test_divdu_8: #_ REGISTER_IN r4 1 #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -71,6 +135,15 @@ test_divdu_8: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF +test_divdu_8_constant: + li r4, 1 + li r5, -1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + test_divdu_9: #_ REGISTER_IN r4 0x8000000000000000 #_ REGISTER_IN r5 -1 @@ -79,3 +152,14 @@ test_divdu_9: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0x8000000000000000 #_ REGISTER_OUT r5 -1 + +# TODO(benvanik): integer overflow (=0) +#test_divdu_9_constant: +# li r4, 1 +# sldi r4, r4, 63 +# li r5, -1 +# divdu r3, r4, r5 +# blr +# #_ REGISTER_OUT r3 0 +# #_ REGISTER_OUT r4 0x8000000000000000 +# #_ REGISTER_OUT r5 -1