diff --git a/src/xenia/gpu/vulkan/pipeline_cache.cc b/src/xenia/gpu/vulkan/pipeline_cache.cc index ca7c37b46..ee1174a72 100644 --- a/src/xenia/gpu/vulkan/pipeline_cache.cc +++ b/src/xenia/gpu/vulkan/pipeline_cache.cc @@ -936,6 +936,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState( auto& state_info = update_rasterization_state_info_; bool dirty = false; + dirty |= regs.primitive_type != primitive_type; dirty |= SetShadowRegister(®s.pa_su_sc_mode_cntl, XE_GPU_REG_PA_SU_SC_MODE_CNTL); dirty |= SetShadowRegister(®s.pa_sc_screen_scissor_tl, @@ -944,6 +945,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState( XE_GPU_REG_PA_SC_SCREEN_SCISSOR_BR); dirty |= SetShadowRegister(®s.multi_prim_ib_reset_index, XE_GPU_REG_VGT_MULTI_PRIM_IB_RESET_INDX); + regs.primitive_type = primitive_type; XXH64_update(&hash_state_, ®s, sizeof(regs)); if (!dirty) { return UpdateStatus::kCompatible; @@ -983,6 +985,10 @@ PipelineCache::UpdateStatus PipelineCache::UpdateRasterizationState( case 2: state_info.cullMode = VK_CULL_MODE_BACK_BIT; break; + case 3: + // Cull both sides? + assert_always(); + break; } if (regs.pa_su_sc_mode_cntl & 0x4) { state_info.frontFace = VK_FRONT_FACE_CLOCKWISE; @@ -1013,6 +1019,8 @@ PipelineCache::UpdateStatus PipelineCache::UpdateMultisampleState() { state_info.pNext = nullptr; state_info.flags = 0; + // PA_SC_AA_CONFIG MSAA_NUM_SAMPLES + // PA_SU_SC_MODE_CNTL MSAA_ENABLE state_info.rasterizationSamples = VK_SAMPLE_COUNT_1_BIT; state_info.sampleShadingEnable = VK_FALSE; state_info.minSampleShading = 0; diff --git a/src/xenia/gpu/vulkan/pipeline_cache.h b/src/xenia/gpu/vulkan/pipeline_cache.h index 3e623f14e..b33c030ed 100644 --- a/src/xenia/gpu/vulkan/pipeline_cache.h +++ b/src/xenia/gpu/vulkan/pipeline_cache.h @@ -205,11 +205,11 @@ class PipelineCache { VkPipelineViewportStateCreateInfo update_viewport_state_info_; struct UpdateRasterizationStateRegisters { + PrimitiveType primitive_type; uint32_t pa_su_sc_mode_cntl; uint32_t pa_sc_screen_scissor_tl; uint32_t pa_sc_screen_scissor_br; uint32_t multi_prim_ib_reset_index; - PrimitiveType prim_type; UpdateRasterizationStateRegisters() { Reset(); } void Reset() { std::memset(this, 0, sizeof(*this)); }