From e5c4590ecf98f6a850aabf34a7a3e1e99d6f37a8 Mon Sep 17 00:00:00 2001
From: gibbed <rick@gibbed.us>
Date: Tue, 9 Jun 2015 19:56:12 -0500
Subject: [PATCH] Few more tests for vsr.

---
 src/xenia/cpu/frontend/test/instr_vsr.s | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/xenia/cpu/frontend/test/instr_vsr.s b/src/xenia/cpu/frontend/test/instr_vsr.s
index 7339007e7..128cfaa66 100644
--- a/src/xenia/cpu/frontend/test/instr_vsr.s
+++ b/src/xenia/cpu/frontend/test/instr_vsr.s
@@ -5,3 +5,19 @@ test_vsr_1:
   blr
   #_ REGISTER_OUT v3 [0FEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFEF]
   #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vsr_2:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vsr v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00011223, 34455667, 78899AAB, BCCDDEEF]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
+
+test_vsr_3:
+  #_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vsr v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]