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CR0 tests for addme.

This commit is contained in:
gibbed 2015-05-14 01:27:06 -05:00
parent ad9b2c792e
commit e4f8818d07
1 changed files with 200 additions and 0 deletions
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200
src/xenia/cpu/frontend/test/instr_addme.s
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@ -165,3 +165,203 @@ test_addme_8_constant:
#_ REGISTER_OUT r3 0 #_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0 #_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1 #_ REGISTER_OUT r6 1
test_addme_cr_1:
#_ REGISTER_IN r4 1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_1_constant:
li r4, 1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_3:
#_ REGISTER_IN r4 12
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_3_constant:
li r4, 12
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_5_constant:
li r4, -1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_7:
#_ REGISTER_IN r4 0
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_7_constant:
li r4, 0
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000