From e348d6361ed89db884446a991391cfa6fdfbed4e Mon Sep 17 00:00:00 2001 From: Triang3l Date: Sat, 12 Dec 2020 14:00:29 +0300 Subject: [PATCH] [PPC] Disable frsqrte tests in a way not breaking the rest --- src/xenia/cpu/ppc/testing/instr_frsqrte.s | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/xenia/cpu/ppc/testing/instr_frsqrte.s b/src/xenia/cpu/ppc/testing/instr_frsqrte.s index f114cb597..df7f0e1d2 100644 --- a/src/xenia/cpu/ppc/testing/instr_frsqrte.s +++ b/src/xenia/cpu/ppc/testing/instr_frsqrte.s @@ -1,21 +1,21 @@ # frsqrte tests disabled because accuracy is CPU dependent. -#test_frsqrte_1: - #_ REGISTER_IN f1 1.0 +test_frsqrte_1: + # _ REGISTER_IN f1 1.0 # frsqrte f1, f1 -# blr - #_ REGISTER_OUT f1 0.99975585937500000 + blr + # _ REGISTER_OUT f1 0.99975585937500000 # want: 0.97 -#test_frsqrte_2: - #_ REGISTER_IN f1 64.0 +test_frsqrte_2: + # _ REGISTER_IN f1 64.0 # frsqrte f1, f1 -# blr - #_ REGISTER_OUT f1 0.12496948242187500 + blr + # _ REGISTER_OUT f1 0.12496948242187500 -#test_frsqrte_3: - #_ REGISTER_IN f1 0.5 +test_frsqrte_3: + # _ REGISTER_IN f1 0.5 # frsqrte f1, f1 -# blr - #_ REGISTER_OUT f1 1.41381835937500000 + blr + # _ REGISTER_OUT f1 1.41381835937500000 # want: 1.375