From e1d771ab9cb1d9531a7324ffd99db2fa20e1d6fb Mon Sep 17 00:00:00 2001 From: Triang3l Date: Wed, 14 Nov 2018 17:02:19 +0300 Subject: [PATCH] [D3D12] GPUTEXTUREFORMAT_11_11_10 support --- .../dxbc/texture_load_r10g11b11_rgba16_cs.cso | Bin 0 -> 7272 bytes .../dxbc/texture_load_r10g11b11_rgba16_cs.h | 610 ++++++++++++++++ .../dxbc/texture_load_r10g11b11_rgba16_cs.txt | 191 +++++ ...texture_load_r10g11b11_rgba16_snorm_cs.cso | Bin 0 -> 8092 bytes .../texture_load_r10g11b11_rgba16_snorm_cs.h | 679 ++++++++++++++++++ ...texture_load_r10g11b11_rgba16_snorm_cs.txt | 214 ++++++ .../dxbc/texture_tile_r10g11b11_rgba16_cs.cso | Bin 0 -> 4976 bytes .../dxbc/texture_tile_r10g11b11_rgba16_cs.h | 419 +++++++++++ .../dxbc/texture_tile_r10g11b11_rgba16_cs.txt | 151 ++++ .../texture_load_r10g11b11_rgba16.cs.hlsl | 47 ++ ...exture_load_r10g11b11_rgba16_snorm.cs.hlsl | 33 + .../texture_tile_r10g11b11_rgba16.cs.hlsl | 42 ++ src/xenia/gpu/d3d12/texture_cache.cc | 23 +- src/xenia/gpu/d3d12/texture_cache.h | 3 + 14 files changed, 2406 insertions(+), 6 deletions(-) create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.cso create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.h create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.txt create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_snorm_cs.cso create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_snorm_cs.h create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_snorm_cs.txt create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_tile_r10g11b11_rgba16_cs.cso create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_tile_r10g11b11_rgba16_cs.h create mode 100644 src/xenia/gpu/d3d12/shaders/dxbc/texture_tile_r10g11b11_rgba16_cs.txt create mode 100644 src/xenia/gpu/d3d12/shaders/texture_load_r10g11b11_rgba16.cs.hlsl create mode 100644 src/xenia/gpu/d3d12/shaders/texture_load_r10g11b11_rgba16_snorm.cs.hlsl create mode 100644 src/xenia/gpu/d3d12/shaders/texture_tile_r10g11b11_rgba16.cs.hlsl diff --git a/src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.cso b/src/xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.cso new file mode 100644 index 0000000000000000000000000000000000000000..508658975e4555524d38dc30a3271df8abacb41a GIT binary patch literal 7272 zcmbuEO^97*8OP6kleyEGq&B8)lqlxfsnCX~Oc9LR<*C*X5v4M8riG;;#OG=bZoC=bX9M5&DGZz8}x` z$NQdhCYNqJfAJrG{`H4nd-cnEzdH5955D;NFBUpQQLMkWC}uQ1BYZ@Y$A!-b|MZ@s zxO(aG;$Myy1$_Sz9ua;_*qK?nh|n)Zd-&l?A7Jm@!Y68cT;p*e@EhT*uq#B5AW|ETtB^3*(kR}5Kvhxyko{_VS}{_^U|uwSgbG}u`yc6WEx(dwhvNm3l(Z*q9D zp6!j%&GiGc^?^;arAo?Vq2b0?%J%JV4vV`RTcf9o-A?IOU7+BPr(YGRZDC`${PbF} zIv8vgii@bG$MxF@@}(QAn}eHQ8XnNy-&)&P+1lz48>A|u!_i=8<#vDhrH!@G`to{z z(;P8Dn7Mwb7wFd+#2b!hJe5>{T^={&Bn%mJDnZDKlUt7p-zR&2t?Avl%3k-Cu|3XfPdxaJPp7{=rfFHm!5K%leb9X7 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12 Size: 4 +// uint3 xe_texture_load_size_texels; // Offset: 16 Size: 12 [unused] +// bool xe_texture_load_is_3d; // Offset: 28 Size: 4 +// uint3 xe_texture_load_size_blocks; // Offset: 32 Size: 12 +// uint xe_texture_load_endianness; // Offset: 44 Size: 4 +// uint2 xe_texture_guest_storage_width_height;// Offset: 48 Size: 8 +// uint xe_texture_load_guest_format; // Offset: 56 Size: 4 [unused] +// uint3 xe_texture_load_guest_mip_offset;// Offset: 64 Size: 12 +// +// } +// +// +// Resource Bindings: +// +// Name Type Format Dim ID HLSL Bind Count +// ------------------------------ ---------- ------- ----------- ------- -------------- ------ +// xe_texture_load_source texture byte r/o T0 t0 1 +// xe_texture_load_dest UAV byte r/w U0 u0 1 +// XeTextureLoadConstants cbuffer NA NA CB0 cb0 1 +// +// +// +// Input signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// no Input +// +// Output signature: +// +// Name Index Mask Register SysValue Format Used +// -------------------- ----- ------ -------- -------- ------- ------ +// no Output +cs_5_1 +dcl_globalFlags refactoringAllowed +dcl_constantbuffer CB0[0:0][5], immediateIndexed, space=0 +dcl_resource_raw T0[0:0], space=0 +dcl_uav_raw U0[0:0], space=0 +dcl_input vThreadID.xyz +dcl_temps 9 +dcl_thread_group 8, 32, 1 +ishl r0.x, vThreadID.x, l(2) +mov r0.yz, vThreadID.yyzy +uge r1.xyz, r0.xyzx, CB0[0][2].xyzx +or r0.w, r1.y, r1.x +or r0.w, r1.z, r0.w +if_nz r0.w + ret +endif +iadd r0.yzw, r0.xxyz, CB0[0][4].xxyz +ieq r1.x, CB0[0][0].y, l(-1) +if_nz r1.x + if_nz CB0[0][1].w + iadd r1.xyzw, r0.yyyy, l(0, 1, 2, 3) + ushr r2.xyz, r0.wzzw, l(2, 4, 3, 0) + ushr r3.xy, CB0[0][3].yxyy, l(4, 5, 0, 0) + imad r2.y, r2.x, r3.x, r2.y + iadd r2.x, r2.z, r2.x + bfi r2.z, l(1), l(1), r2.x, l(0) + ushr r4.xyzw, r1.xyzw, l(3, 3, 3, 3) + iadd r4.xyzw, r2.zzzz, r4.xyzw + bfi r4.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r4.xyzw, l(0, 0, 0, 0) + bfi r4.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r2.xxxx, r4.xyzw + ishl r2.x, r0.z, l(10) + and r2.x, r2.x, l(6144) + bfi r5.xyzw, l(3, 3, 3, 3), l(8, 8, 8, 8), r1.xyzw, r2.xxxx + ushr r5.xyzw, r5.xyzw, l(6, 6, 6, 6) + ushr r1.xyzw, r1.xyzw, l(5, 5, 5, 5) + imad r1.xyzw, r2.yyyy, r3.yyyy, r1.xyzw + and r2.xyzw, r5.xyzw, l(112, 112, 112, 112) + bfi r3.xyzw, l(20, 20, 20, 20), l(10, 10, 10, 10), r1.xyzw, l(0, 0, 0, 0) + imad r3.xyzw, r2.xyzw, l(2, 2, 2, 2), r3.xyzw + bfi r3.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r3.xyzw + bfi r3.xyzw, l(2, 2, 2, 2), l(8, 8, 8, 8), r0.wwww, r3.xyzw + bfi r6.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r3.xyzw + ubfe r3.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r3.xyzw + and r7.xyzw, r4.xyzw, l(6, 6, 6, 6) + bfi r4.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r4.xyzw, l(0, 0, 0, 0) + imad r3.xyzw, r3.xyzw, l(32, 32, 32, 32), r4.xyzw + imad r3.xyzw, r7.xyzw, l(4, 4, 4, 4), r3.xyzw + bfi r1.xyzw, l(20, 20, 20, 20), l(13, 13, 13, 13), r1.xyzw, l(0, 0, 0, 0) + imad r1.xyzw, r2.xyzw, l(16, 16, 16, 16), r1.xyzw + bfi r1.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r1.xyzw + bfi r1.xyzw, l(2, 2, 2, 2), l(11, 11, 11, 11), r0.wwww, r1.xyzw + bfi r1.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r1.xyzw + bfi r1.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r3.xyzw, r1.xyzw + bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r6.xyzw, r1.xyzw + else + iadd r2.xyzw, r0.yyyy, l(0, 1, 2, 3) + ushr r3.xyzw, r2.xyzw, l(5, 5, 5, 5) + ushr r4.xy, r0.zzzz, l(5, 2, 0, 0) + iadd r4.z, CB0[0][3].x, l(31) + ushr r4.z, r4.z, l(5) + imad r3.xyzw, r4.xxxx, r4.zzzz, r3.xyzw + ishl r4.xz, r0.zzzz, l(4, 0, 7, 0) + and r4.xz, r4.xxzx, l(224, 0, 2048, 0) + bfi r5.xyzw, l(3, 3, 3, 3), l(2, 2, 2, 2), r2.xyzw, r4.xxxx + ishl r4.x, r4.x, l(1) + bfi r6.xyzw, l(3, 3, 3, 3), l(3, 3, 3, 3), r2.xyzw, r4.xxxx + and r6.xyzw, r6.xyzw, l(480, 480, 480, 480) + bfi r7.xyzw, l(23, 23, 23, 23), l(9, 9, 9, 9), r3.xyzw, r6.xyzw + bfi r7.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r5.xyzw, r7.xyzw + bfi r7.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.zzzz, r7.xyzw + ishl r8.xyzw, r6.xyzw, l(3, 3, 3, 3) + bfi r8.xyzw, l(23, 23, 23, 23), l(12, 12, 12, 12), r3.xyzw, r8.xyzw + bfi r8.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r5.xyzw, r8.xyzw + bfi r8.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.zzzz, r8.xyzw + bfi r8.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r4.zzzz, r8.xyzw + ishl r6.xyzw, r6.xyzw, l(2, 2, 2, 2) + bfi r3.xyzw, l(23, 23, 23, 23), l(11, 11, 11, 11), r3.xyzw, r6.xyzw + bfi r3.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r5.xyzw, r3.xyzw + bfi r3.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.zzzz, r3.xyzw + and r3.xyzw, r3.xyzw, l(1792, 1792, 1792, 1792) + iadd r3.xyzw, r8.xyzw, r3.xyzw + ushr r2.xyzw, r2.xyzw, l(3, 3, 3, 3) + and r4.x, r4.y, l(2) + iadd r2.xyzw, r2.xyzw, r4.xxxx + bfi r2.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r2.xyzw, l(0, 0, 0, 0) + iadd r2.xyzw, r3.xyzw, r2.xyzw + bfi r1.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r7.xyzw, r2.xyzw + endif +else + ishl r0.y, r0.y, l(2) + iadd r2.x, CB0[0][2].y, l(31) + and r2.x, r2.x, l(-32) + imad r0.z, r0.w, r2.x, r0.z + imad r0.y, r0.z, CB0[0][0].y, r0.y + iadd r1.xyzw, r0.yyyy, l(0, 4, 8, 12) +endif +iadd r1.xyzw, r1.xyzw, CB0[0][0].xxxx +ld_raw r2.z, r1.x, T0[0].xxxx +ld_raw r2.w, r1.y, T0[0].xxxx +ld_raw r2.x, r1.z, T0[0].xxxx +ld_raw r2.y, r1.w, T0[0].xxxx +ushr r0.y, CB0[0][2].w, l(1) +xor r0.y, r0.y, CB0[0][2].w +and r0.y, r0.y, l(1) +if_nz r0.y + ishl r1.xyzw, r2.zwxy, l(8, 8, 8, 8) + and r1.xyzw, r1.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00) + ushr r3.xyzw, r2.zwxy, l(8, 8, 8, 8) + and r3.xyzw, r3.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff) + iadd r2.xyzw, r1.zwxy, r3.zwxy +endif +and r0.y, CB0[0][2].w, l(2) +if_nz r0.y + ushr r1.xyzw, r2.zwxy, l(16, 16, 16, 16) + bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r1.zwxy + mov r1.xy, r2.zwzz +else + mov r1.xy, r2.zwzz +endif +ishl r0.x, r0.x, l(3) +imad r0.y, vThreadID.z, CB0[0][2].y, vThreadID.y +imad r0.x, r0.y, CB0[0][0].w, r0.x +iadd r0.x, r0.x, CB0[0][0].z +ushr r1.zw, r1.xxxy, l(0, 0, 21, 21) +bfi r3.xyzw, l(10, 27, 10, 27), l(6, 5, 6, 5), r1.xzyw, l(0, 0, 0, 0) +ubfe r4.xyzw, l(6, 5, 6, 5), l(4, 27, 4, 27), r1.xxyy +iadd r3.xyzw, r3.xyzw, r4.xyzw +ishl r0.yz, r1.xxyx, l(0, 11, 11, 0) +and r1.xy, r1.xyxx, l(0x001f0000, 0x001f0000, 0, 0) +bfi r0.yz, l(0, 21, 21, 0), l(0, 0, 0, 0), r1.xxyx, r0.yyzy +iadd r1.xz, r0.yyzy, r3.xxzx +iadd r1.yw, r3.yyyw, l(0, 0xffff0000, 0, 0xffff0000) +store_raw U0[0].xyzw, r0.x, r1.xyzw +ushr r2.zw, r2.xxxy, l(0, 0, 21, 21) +bfi r1.xyzw, l(10, 27, 10, 27), l(6, 5, 6, 5), r2.xzyw, l(0, 0, 0, 0) +ubfe r3.xyzw, l(6, 5, 6, 5), l(4, 27, 4, 27), r2.xxyy +iadd r1.xyzw, r1.xyzw, r3.xyzw +ishl r0.yz, r2.xxyx, l(0, 11, 11, 0) +and r2.xy, r2.xyxx, l(0x001f0000, 0x001f0000, 0, 0) +bfi r0.yz, l(0, 21, 21, 0), l(0, 0, 0, 0), r2.xxyx, r0.yyzy +iadd r2.xz, r0.yyzy, r1.xxzx +iadd r2.yw, r1.yyyw, l(0, 0xffff0000, 0, 0xffff0000) +iadd r0.y, r0.x, l(16) +store_raw U0[0].xyzw, r0.y, r2.xyzw +ret +// Approximately 137 instruction slots used diff --git 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zZM@~WcyU;MHriU|%98rB91L$YHDAVOqYq`am@~a;9OBRJVmQoJFa3===-iIq^BUAu z0UrdGqVJBaAYcSTZp1+H884b%b!WkoP#Lf}Dg2m1lYw&|qoiXe_fQhOh6CbM27<|<4jyQSdj4}GK z(f{cgyH}mFMJ$xqH$S~+cpsQ4o--e?Z1~~%_V(!CzB8-N2srv1@!{TQMAPg02d;b> z7>At^5Iz)Rl*#!}eMU&vIMlP1|Ch4f7c>)UP4Cmg)>A(8=U{x`>@0(`GbD2+^o-Tm z>dweIdewSSeAzzZ8%cd*iPmf?yBm$uhiFSNRW{o%i=pbAjLVDlKJnPz;-P#_=zp-R r0Slk$Nj*=`JU{b^>= xe_texture_load_size_blocks)) { + return; + } + uint4 block_offsets_guest = + XeTextureLoadGuestBlockOffsets(block_index, 4u, 2u); + uint4 blocks = uint4(xe_texture_load_source.Load(block_offsets_guest.x), + xe_texture_load_source.Load(block_offsets_guest.y), + xe_texture_load_source.Load(block_offsets_guest.z), + xe_texture_load_source.Load(block_offsets_guest.w)); + blocks = XeByteSwap(blocks, xe_texture_load_endianness); + uint block_offset_host = XeTextureHostLinearOffset( + block_index, xe_texture_load_size_blocks.y, xe_texture_load_host_pitch, + 8u) + xe_texture_load_host_base; + + // First 2 texels. + // Red and blue. + uint4 blocks_host = + (((blocks.xxyy >> uint2(0u, 21u).xyxy) & uint2(1023u, 2047u).xyxy) << + uint2(6u, 5u).xyxy) | + ((blocks.xxyy >> uint2(4u, 27u).xyxy) & uint2(63u, 31u).xyxy); + // Green. The 5 bits to be duplicated to the bottom are already at 16. + blocks_host.xz |= ((blocks.xy & (2047u << 10u)) << (21u - 10u)) | + (blocks.xy & (31u << 16u)); + // Alpha. + blocks_host.yw |= 0xFFFF0000u; + xe_texture_load_dest.Store4(block_offset_host, blocks_host); + + // Second 2 texels. + // Red and blue. + blocks_host = + (((blocks.zzww >> uint2(0u, 21u).xyxy) & uint2(1023u, 2047u).xyxy) << + uint2(6u, 5u).xyxy) | + ((blocks.zzww >> uint2(4u, 27u).xyxy) & uint2(63u, 31u).xyxy); + // Green. The 5 bits to be duplicated to the bottom are already at 16. + blocks_host.xz |= ((blocks.zw & (2047u << 10u)) << (21u - 10u)) | + (blocks.zw & (31u << 16u)); + // Alpha. + blocks_host.yw |= 0xFFFF0000u; + xe_texture_load_dest.Store4(block_offset_host + 16u, blocks_host); +} diff --git a/src/xenia/gpu/d3d12/shaders/texture_load_r10g11b11_rgba16_snorm.cs.hlsl b/src/xenia/gpu/d3d12/shaders/texture_load_r10g11b11_rgba16_snorm.cs.hlsl new file mode 100644 index 000000000..2a337eda5 --- /dev/null +++ b/src/xenia/gpu/d3d12/shaders/texture_load_r10g11b11_rgba16_snorm.cs.hlsl @@ -0,0 +1,33 @@ +#include "pixel_formats.hlsli" +#include "texture_load.hlsli" + +[numthreads(8, 32, 1)] +void main(uint3 xe_thread_id : SV_DispatchThreadID) { + // 1 thread = 4 uint R10G11B11_SNORM texels to RGBA16. + uint3 block_index = xe_thread_id; + block_index.x <<= 2u; + [branch] if (any(block_index >= xe_texture_load_size_blocks)) { + return; + } + uint4 block_offsets_guest = + XeTextureLoadGuestBlockOffsets(block_index, 4u, 2u); + uint4 blocks = uint4(xe_texture_load_source.Load(block_offsets_guest.x), + xe_texture_load_source.Load(block_offsets_guest.y), + xe_texture_load_source.Load(block_offsets_guest.z), + xe_texture_load_source.Load(block_offsets_guest.w)); + blocks = XeByteSwap(blocks, xe_texture_load_endianness); + uint block_offset_host = XeTextureHostLinearOffset( + block_index, xe_texture_load_size_blocks.y, xe_texture_load_host_pitch, + 8u) + xe_texture_load_host_base; + + // Expand two's complement. + uint4 blocks_host_rg = + XeSNorm10To16(blocks & 1023u) | XeSNorm11To16((blocks >> 10u) & 2047u); + uint4 blocks_host_ba = XeSNorm11To16(blocks >> 21u) | 0x7FFF0000u; + + // Store the texels. + xe_texture_load_dest.Store4(block_offset_host, + uint4(blocks_host_rg.xy, blocks_host_ba.xy).xzyw); + xe_texture_load_dest.Store4(block_offset_host + 16u, + uint4(blocks_host_rg.zw, blocks_host_ba.zw).xzyw); +} diff --git a/src/xenia/gpu/d3d12/shaders/texture_tile_r10g11b11_rgba16.cs.hlsl b/src/xenia/gpu/d3d12/shaders/texture_tile_r10g11b11_rgba16.cs.hlsl new file mode 100644 index 000000000..160a58d65 --- /dev/null +++ b/src/xenia/gpu/d3d12/shaders/texture_tile_r10g11b11_rgba16.cs.hlsl @@ -0,0 +1,42 @@ +#include "texture_tile.hlsli" + +RWByteAddressBuffer xe_texture_tile_dest : register(u0); + +[numthreads(8, 32, 1)] +void main(uint3 xe_thread_id : SV_DispatchThreadID) { + // 1 thread = 4 texels. + uint2 texture_size = (xe_texture_tile_size >> uint2(0u, 16u)) & 0xFFFFu; + uint2 texel_index = xe_thread_id.xy; + texel_index.x <<= 2u; + [branch] if (any(texel_index >= texture_size)) { + return; + } + + uint4 texel_addresses = xe_texture_tile_guest_base + XeTextureTiledOffset2D( + ((xe_texture_tile_offset >> uint2(0u, 16u)) & 0xFFFFu) + texel_index, + xe_texture_tile_endian_format_guest_pitch >> 9u, 2u); + bool3 texels_inside = uint3(1u, 2u, 3u) + texel_index.x < texture_size.x; + + uint texels_host_offset = xe_texture_tile_host_base + texel_index.y * + xe_texture_tile_host_pitch + texel_index.x * 8u; + uint4 texels_host = xe_texture_tile_source.Load4(texels_host_offset); + uint2 texels = XeByteSwap( + ((texels_host.xz >> 6u) & 1023u) | ((texels_host.xz >> 21u) << 10u) | + ((texels_host.yw >> 5u) << 21u), + xe_texture_tile_endian_format_guest_pitch); + xe_texture_tile_dest.Store(texel_addresses.x, texels.x); + [branch] if (texels_inside.x) { + xe_texture_tile_dest.Store(texel_addresses.y, texels.y); + [branch] if (texels_inside.y) { + texels_host = xe_texture_tile_source.Load4(texels_host_offset + 16u); + texels = XeByteSwap( + ((texels_host.xz >> 6u) & 1023u) | ((texels_host.xz >> 21u) << 10u) | + ((texels_host.yw >> 5u) << 21u), + xe_texture_tile_endian_format_guest_pitch); + xe_texture_tile_dest.Store(texel_addresses.z, texels.x); + [branch] if (texels_inside.z) { + xe_texture_tile_dest.Store(texel_addresses.w, texels.y); + } + } + } +} diff --git a/src/xenia/gpu/d3d12/texture_cache.cc b/src/xenia/gpu/d3d12/texture_cache.cc index 8ab17a7ec..e9a1f61a0 100644 --- a/src/xenia/gpu/d3d12/texture_cache.cc +++ b/src/xenia/gpu/d3d12/texture_cache.cc @@ -42,6 +42,8 @@ namespace d3d12 { #include "xenia/gpu/d3d12/shaders/dxbc/texture_load_dxt3a_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_load_dxt5_rgba8_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_load_dxt5a_r8_cs.h" +#include "xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_cs.h" +#include "xenia/gpu/d3d12/shaders/dxbc/texture_load_r10g11b11_rgba16_snorm_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_load_r11g11b10_rgba16_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_load_r11g11b10_rgba16_snorm_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_128bpp_cs.h" @@ -50,6 +52,7 @@ namespace d3d12 { #include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_32bpp_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_64bpp_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_8bpp_cs.h" +#include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_r10g11b11_rgba16_cs.h" #include "xenia/gpu/d3d12/shaders/dxbc/texture_tile_r11g11b10_rgba16_cs.h" constexpr uint32_t TextureCache::LoadConstants::kGuestPitchTiled; @@ -130,9 +133,10 @@ const TextureCache::HostFormat TextureCache::host_formats_[64] = { LoadMode::kR11G11B10ToRGBA16SNorm, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_R16G16B16A16_UNORM, ResolveTileMode::kR11G11B10AsRGBA16}, // k_11_11_10 - {DXGI_FORMAT_UNKNOWN, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, - DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, - LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, ResolveTileMode::kUnknown}, + {DXGI_FORMAT_R16G16B16A16_TYPELESS, DXGI_FORMAT_R16G16B16A16_UNORM, + LoadMode::kR10G11B11ToRGBA16, DXGI_FORMAT_R16G16B16A16_SNORM, + LoadMode::kR10G11B11ToRGBA16SNorm, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, + DXGI_FORMAT_R16G16B16A16_UNORM, ResolveTileMode::kR10G11B11AsRGBA16}, // k_DXT1 {DXGI_FORMAT_BC1_UNORM, DXGI_FORMAT_BC1_UNORM, LoadMode::k64bpb, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_R8G8B8A8_UNORM, @@ -300,9 +304,10 @@ const TextureCache::HostFormat TextureCache::host_formats_[64] = { LoadMode::kR11G11B10ToRGBA16SNorm, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_R16G16B16A16_UNORM, ResolveTileMode::kR11G11B10AsRGBA16}, // k_11_11_10_AS_16_16_16_16 - {DXGI_FORMAT_UNKNOWN, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, - DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, - LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, ResolveTileMode::kUnknown}, + {DXGI_FORMAT_R16G16B16A16_TYPELESS, DXGI_FORMAT_R16G16B16A16_UNORM, + LoadMode::kR10G11B11ToRGBA16, DXGI_FORMAT_R16G16B16A16_SNORM, + LoadMode::kR10G11B11ToRGBA16SNorm, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, + DXGI_FORMAT_R16G16B16A16_UNORM, ResolveTileMode::kR10G11B11AsRGBA16}, // k_32_32_32_FLOAT {DXGI_FORMAT_UNKNOWN, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, LoadMode::kUnknown, DXGI_FORMAT_UNKNOWN, @@ -348,6 +353,10 @@ const TextureCache::LoadModeInfo TextureCache::load_mode_info_[] = { sizeof(texture_load_r11g11b10_rgba16_cs)}, {texture_load_r11g11b10_rgba16_snorm_cs, sizeof(texture_load_r11g11b10_rgba16_snorm_cs)}, + {texture_load_r10g11b11_rgba16_cs, + sizeof(texture_load_r10g11b11_rgba16_cs)}, + {texture_load_r10g11b11_rgba16_snorm_cs, + sizeof(texture_load_r10g11b11_rgba16_snorm_cs)}, {texture_load_dxt1_rgba8_cs, sizeof(texture_load_dxt1_rgba8_cs)}, {texture_load_dxt3_rgba8_cs, sizeof(texture_load_dxt3_rgba8_cs)}, {texture_load_dxt5_rgba8_cs, sizeof(texture_load_dxt5_rgba8_cs)}, @@ -375,6 +384,8 @@ const TextureCache::ResolveTileModeInfo DXGI_FORMAT_R16_UINT, 1}, {texture_tile_r11g11b10_rgba16_cs, sizeof(texture_tile_r11g11b10_rgba16_cs), DXGI_FORMAT_UNKNOWN, 0}, + {texture_tile_r10g11b11_rgba16_cs, + sizeof(texture_tile_r10g11b11_rgba16_cs), DXGI_FORMAT_UNKNOWN, 0}, }; TextureCache::TextureCache(D3D12CommandProcessor* command_processor, diff --git a/src/xenia/gpu/d3d12/texture_cache.h b/src/xenia/gpu/d3d12/texture_cache.h index c9571a0a1..1e00fb88c 100644 --- a/src/xenia/gpu/d3d12/texture_cache.h +++ b/src/xenia/gpu/d3d12/texture_cache.h @@ -149,6 +149,8 @@ class TextureCache { k128bpb, kR11G11B10ToRGBA16, kR11G11B10ToRGBA16SNorm, + kR10G11B11ToRGBA16, + kR10G11B11ToRGBA16SNorm, kDXT1ToRGBA8, kDXT3ToRGBA8, kDXT5ToRGBA8, @@ -181,6 +183,7 @@ class TextureCache { // supported on Nvidia. k16bppRGBA, kR11G11B10AsRGBA16, + kR10G11B11AsRGBA16, kCount,