From df600a105af430495f2dd884e530394dd7c2884c Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Thu, 14 May 2015 14:42:54 -0700 Subject: [PATCH] Fixing constant compare. --- .../cpu/frontend/test/bin/instr_addc.bin | Bin 60 -> 404 bytes .../cpu/frontend/test/bin/instr_addc.dis | 152 ++++++++++++-- .../cpu/frontend/test/bin/instr_addc.map | 25 ++- .../cpu/frontend/test/bin/instr_adde.bin | Bin 440 -> 1040 bytes .../cpu/frontend/test/bin/instr_adde.dis | 190 ++++++++++++++++++ .../cpu/frontend/test/bin/instr_adde.map | 20 ++ .../cpu/frontend/test/bin/instr_addic.bin | Bin 24 -> 128 bytes .../cpu/frontend/test/bin/instr_addic.dis | 46 ++++- .../cpu/frontend/test/bin/instr_addic.map | 8 +- .../cpu/frontend/test/bin/instr_addis.bin | Bin 0 -> 112 bytes .../cpu/frontend/test/bin/instr_addis.dis | 49 +++++ .../cpu/frontend/test/bin/instr_addis.map | 10 + .../cpu/frontend/test/bin/instr_addme.bin | Bin 320 -> 704 bytes .../cpu/frontend/test/bin/instr_addme.dis | 128 ++++++++++++ .../cpu/frontend/test/bin/instr_addme.map | 16 ++ .../cpu/frontend/test/bin/instr_addze.bin | Bin 320 -> 704 bytes .../cpu/frontend/test/bin/instr_addze.dis | 128 ++++++++++++ .../cpu/frontend/test/bin/instr_addze.map | 16 ++ src/xenia/cpu/frontend/test/bin/instr_and.bin | Bin 0 -> 304 bytes src/xenia/cpu/frontend/test/bin/instr_and.dis | 117 +++++++++++ src/xenia/cpu/frontend/test/bin/instr_and.map | 20 ++ .../cpu/frontend/test/bin/instr_andc.bin | Bin 0 -> 304 bytes .../cpu/frontend/test/bin/instr_andc.dis | 117 +++++++++++ .../cpu/frontend/test/bin/instr_andc.map | 20 ++ .../cpu/frontend/test/bin/instr_andi.bin | Bin 0 -> 140 bytes .../cpu/frontend/test/bin/instr_andi.dis | 56 ++++++ .../cpu/frontend/test/bin/instr_andi.map | 10 + .../cpu/frontend/test/bin/instr_andis.bin | Bin 0 -> 140 bytes .../cpu/frontend/test/bin/instr_andis.dis | 56 ++++++ .../cpu/frontend/test/bin/instr_andis.map | 10 + src/xenia/cpu/frontend/test/bin/instr_cmp.bin | Bin 0 -> 316 bytes src/xenia/cpu/frontend/test/bin/instr_cmp.dis | 116 +++++++++++ src/xenia/cpu/frontend/test/bin/instr_cmp.map | 18 ++ .../cpu/frontend/test/bin/instr_cmpi.bin | Bin 0 -> 216 bytes .../cpu/frontend/test/bin/instr_cmpi.dis | 83 ++++++++ .../cpu/frontend/test/bin/instr_cmpi.map | 14 ++ .../cpu/frontend/test/bin/instr_cmpl.bin | Bin 0 -> 360 bytes .../cpu/frontend/test/bin/instr_cmpl.dis | 131 ++++++++++++ .../cpu/frontend/test/bin/instr_cmpl.map | 20 ++ .../cpu/frontend/test/bin/instr_cmpli.bin | Bin 0 -> 216 bytes .../cpu/frontend/test/bin/instr_cmpli.dis | 83 ++++++++ .../cpu/frontend/test/bin/instr_cmpli.map | 14 ++ .../cpu/frontend/test/bin/instr_extsb.bin | Bin 0 -> 200 bytes .../cpu/frontend/test/bin/instr_extsb.dis | 83 ++++++++ .../cpu/frontend/test/bin/instr_extsb.map | 16 ++ .../cpu/frontend/test/bin/instr_extsh.bin | Bin 0 -> 216 bytes .../cpu/frontend/test/bin/instr_extsh.dis | 87 ++++++++ .../cpu/frontend/test/bin/instr_extsh.map | 16 ++ .../cpu/frontend/test/bin/instr_extsw.bin | Bin 0 -> 224 bytes .../cpu/frontend/test/bin/instr_extsw.dis | 89 ++++++++ .../cpu/frontend/test/bin/instr_extsw.map | 16 ++ src/xenia/cpu/frontend/test/instr_andi.s | 32 +-- src/xenia/cpu/frontend/test/instr_andis.s | 32 +-- src/xenia/cpu/hir/hir_builder.cc | 3 +- src/xenia/cpu/hir/value.cc | 138 ++++++++++++- src/xenia/cpu/hir/value.h | 6 + 56 files changed, 2127 insertions(+), 64 deletions(-) create mode 100644 src/xenia/cpu/frontend/test/bin/instr_addis.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_addis.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_addis.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_and.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_and.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_and.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andc.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andc.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andc.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andi.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andi.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andi.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andis.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andis.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_andis.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmp.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmp.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmp.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpi.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpi.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpi.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpl.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpl.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpl.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpli.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpli.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_cmpli.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsb.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsb.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsb.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsh.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsh.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsh.map create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsw.bin create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsw.dis create mode 100644 src/xenia/cpu/frontend/test/bin/instr_extsw.map diff --git a/src/xenia/cpu/frontend/test/bin/instr_addc.bin b/src/xenia/cpu/frontend/test/bin/instr_addc.bin index 49641167a1cf4301cc879d44b56694f9af2d8357..698a4c6b2e04f15988d8841e21090c3c2ec6f33e 100644 GIT binary patch literal 404 zcmb%n--` diff --git a/src/xenia/cpu/frontend/test/bin/instr_addc.dis b/src/xenia/cpu/frontend/test/bin/instr_addc.dis index 6130d06c0..c54a9358a 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addc.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_addc.dis @@ -5,22 +5,142 @@ Disassembly of section .text: 100004: 7c c0 01 14 adde r6,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 64 28 14 addc r3,r4,r5 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 38 a0 00 02 li r5,2 + 100014: 7c 64 28 14 addc r3,r4,r5 + 100018: 7c c0 01 14 adde r6,r0,r0 + 10001c: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 64 28 14 addc r3,r4,r5 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100020 : + 100020: 7c 64 28 14 addc r3,r4,r5 + 100024: 7c c0 01 14 adde r6,r0,r0 + 100028: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 64 28 14 addc r3,r4,r5 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010002c : + 10002c: 38 80 ff ff li r4,-1 + 100030: 38 a0 00 00 li r5,0 + 100034: 7c 64 28 14 addc r3,r4,r5 + 100038: 7c c0 01 14 adde r6,r0,r0 + 10003c: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 64 28 14 addc r3,r4,r5 - 100034: 7c c0 01 14 adde r6,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100040 : + 100040: 7c 64 28 14 addc r3,r4,r5 + 100044: 7c c0 01 14 adde r6,r0,r0 + 100048: 4e 80 00 20 blr + +000000000010004c : + 10004c: 38 80 ff ff li r4,-1 + 100050: 38 a0 00 01 li r5,1 + 100054: 7c 64 28 14 addc r3,r4,r5 + 100058: 7c c0 01 14 adde r6,r0,r0 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 28 14 addc r3,r4,r5 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 ff ff li r4,-1 + 100070: 38 a0 00 7b li r5,123 + 100074: 7c 64 28 14 addc r3,r4,r5 + 100078: 7c c0 01 14 adde r6,r0,r0 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 7c 64 28 14 addc r3,r4,r5 + 100084: 7c c0 01 14 adde r6,r0,r0 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 38 a0 ff ff li r5,-1 + 100090: 78 a4 f8 42 rldicl r4,r5,63,1 + 100094: 7c 64 28 14 addc r3,r4,r5 + 100098: 7c c0 01 14 adde r6,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 7c 64 28 15 addc. r3,r4,r5 + 1000a4: 7c c0 01 14 adde r6,r0,r0 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 00 01 li r4,1 + 1000b4: 38 a0 00 02 li r5,2 + 1000b8: 7c 64 28 15 addc. r3,r4,r5 + 1000bc: 7c c0 01 14 adde r6,r0,r0 + 1000c0: 7d 80 00 26 mfcr r12 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 7c 64 28 15 addc. r3,r4,r5 + 1000cc: 7c c0 01 14 adde r6,r0,r0 + 1000d0: 7d 80 00 26 mfcr r12 + 1000d4: 4e 80 00 20 blr + +00000000001000d8 : + 1000d8: 38 80 ff ff li r4,-1 + 1000dc: 38 a0 00 00 li r5,0 + 1000e0: 7c 64 28 15 addc. r3,r4,r5 + 1000e4: 7c c0 01 14 adde r6,r0,r0 + 1000e8: 7d 80 00 26 mfcr r12 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 7c 64 28 15 addc. r3,r4,r5 + 1000f4: 7c c0 01 14 adde r6,r0,r0 + 1000f8: 7d 80 00 26 mfcr r12 + 1000fc: 4e 80 00 20 blr + +0000000000100100 : + 100100: 38 80 ff ff li r4,-1 + 100104: 38 a0 00 01 li r5,1 + 100108: 7c 64 28 15 addc. r3,r4,r5 + 10010c: 7c c0 01 14 adde r6,r0,r0 + 100110: 7d 80 00 26 mfcr r12 + 100114: 4e 80 00 20 blr + +0000000000100118 : + 100118: 7c 64 28 15 addc. r3,r4,r5 + 10011c: 7c c0 01 14 adde r6,r0,r0 + 100120: 7d 80 00 26 mfcr r12 + 100124: 4e 80 00 20 blr + +0000000000100128 : + 100128: 38 80 ff ff li r4,-1 + 10012c: 38 a0 00 7b li r5,123 + 100130: 7c 64 28 15 addc. r3,r4,r5 + 100134: 7c c0 01 14 adde r6,r0,r0 + 100138: 7d 80 00 26 mfcr r12 + 10013c: 4e 80 00 20 blr + +0000000000100140 : + 100140: 7c 64 28 15 addc. r3,r4,r5 + 100144: 7c c0 01 14 adde r6,r0,r0 + 100148: 7d 80 00 26 mfcr r12 + 10014c: 4e 80 00 20 blr + +0000000000100150 : + 100150: 38 a0 ff ff li r5,-1 + 100154: 78 a4 f8 42 rldicl r4,r5,63,1 + 100158: 7c 64 28 15 addc. r3,r4,r5 + 10015c: 7c c0 01 14 adde r6,r0,r0 + 100160: 7d 80 00 26 mfcr r12 + 100164: 4e 80 00 20 blr + +0000000000100168 : + 100168: 7c 64 28 15 addc. r3,r4,r5 + 10016c: 7c c0 01 14 adde r6,r0,r0 + 100170: 7d 80 00 26 mfcr r12 + 100174: 4e 80 00 20 blr + +0000000000100178 : + 100178: 38 80 ff ff li r4,-1 + 10017c: 78 84 f8 42 rldicl r4,r4,63,1 + 100180: 38 a0 00 02 li r5,2 + 100184: 7c 64 28 15 addc. r3,r4,r5 + 100188: 7c c0 01 14 adde r6,r0,r0 + 10018c: 7d 80 00 26 mfcr r12 + 100190: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addc.map b/src/xenia/cpu/frontend/test/bin/instr_addc.map index 4ec8531ad..b40c830af 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addc.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addc.map @@ -1,5 +1,22 @@ 0000000000000000 t test_addc_1 -000000000000000c t test_addc_2 -0000000000000018 t test_addc_3 -0000000000000024 t test_addc_4 -0000000000000030 t test_addc_5 +000000000000000c t test_addc_1_constant +0000000000000020 t test_addc_2 +000000000000002c t test_addc_2_constant +0000000000000040 t test_addc_3 +000000000000004c t test_addc_3_constant +0000000000000060 t test_addc_4 +000000000000006c t test_addc_4_constant +0000000000000080 t test_addc_5 +000000000000008c t test_addc_5_constant +00000000000000a0 t test_addc_cr_1 +00000000000000b0 t test_addc_cr_1_constant +00000000000000c8 t test_addc_cr_2 +00000000000000d8 t test_addc_cr_2_constant +00000000000000f0 t test_addc_cr_3 +0000000000000100 t test_addc_cr_3_constant +0000000000000118 t test_addc_cr_4 +0000000000000128 t test_addc_cr_4_constant +0000000000000140 t test_addc_cr_5 +0000000000000150 t test_addc_cr_5_constant +0000000000000168 t test_addc_cr_6 +0000000000000178 t test_addc_cr_6_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_adde.bin b/src/xenia/cpu/frontend/test/bin/instr_adde.bin index 464ddfe7df7976a47a8976080dca6f16d5e7120a..1b29139bf24f83fe957944459b1afae0f66c1dcb 100644 GIT binary patch literal 1040 zcmb{U+rXfP7JnFWXzs_5#}S_x>VR&?5QByRD1I^I2-}M_zA??gVm8!XQ2b-6M-4X& gdAMEz>adv&k8|?vttJ#MSnY+S33BX(=_TM_0At-qGynhq delta 7 OcmbQhv4eTT4n_bAOai?C diff --git a/src/xenia/cpu/frontend/test/bin/instr_adde.dis b/src/xenia/cpu/frontend/test/bin/instr_adde.dis index 33c5867a7..367647069 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_adde.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_adde.dis @@ -149,3 +149,193 @@ Disassembly of section .text: 1001ac: 7c 64 29 14 adde r3,r4,r5 1001b0: 7c c0 01 14 adde r6,r0,r0 1001b4: 4e 80 00 20 blr + +00000000001001b8 : + 1001b8: 7c 64 29 15 adde. r3,r4,r5 + 1001bc: 7d 60 00 26 mfcr r11 + 1001c0: 7c c0 01 15 adde. r6,r0,r0 + 1001c4: 7d 80 00 26 mfcr r12 + 1001c8: 4e 80 00 20 blr + +00000000001001cc : + 1001cc: 38 80 00 01 li r4,1 + 1001d0: 38 a0 00 02 li r5,2 + 1001d4: 7c 64 29 15 adde. r3,r4,r5 + 1001d8: 7d 60 00 26 mfcr r11 + 1001dc: 7c c0 01 15 adde. r6,r0,r0 + 1001e0: 7d 80 00 26 mfcr r12 + 1001e4: 4e 80 00 20 blr + +00000000001001e8 : + 1001e8: 7c 63 1a 78 xor r3,r3,r3 + 1001ec: 7c 63 18 f8 not r3,r3 + 1001f0: 30 63 00 01 addic r3,r3,1 + 1001f4: 7c 64 29 15 adde. r3,r4,r5 + 1001f8: 7d 60 00 26 mfcr r11 + 1001fc: 7c c0 01 15 adde. r6,r0,r0 + 100200: 7d 80 00 26 mfcr r12 + 100204: 4e 80 00 20 blr + +0000000000100208 : + 100208: 38 80 00 01 li r4,1 + 10020c: 38 a0 00 02 li r5,2 + 100210: 7c 63 1a 78 xor r3,r3,r3 + 100214: 7c 63 18 f8 not r3,r3 + 100218: 30 63 00 01 addic r3,r3,1 + 10021c: 7c 64 29 15 adde. r3,r4,r5 + 100220: 7d 60 00 26 mfcr r11 + 100224: 7c c0 01 15 adde. r6,r0,r0 + 100228: 7d 80 00 26 mfcr r12 + 10022c: 4e 80 00 20 blr + +0000000000100230 : + 100230: 7c 64 29 15 adde. r3,r4,r5 + 100234: 7d 60 00 26 mfcr r11 + 100238: 7c c0 01 15 adde. r6,r0,r0 + 10023c: 7d 80 00 26 mfcr r12 + 100240: 4e 80 00 20 blr + +0000000000100244 : + 100244: 38 80 ff ff li r4,-1 + 100248: 38 a0 00 00 li r5,0 + 10024c: 7c 64 29 15 adde. r3,r4,r5 + 100250: 7d 60 00 26 mfcr r11 + 100254: 7c c0 01 15 adde. r6,r0,r0 + 100258: 7d 80 00 26 mfcr r12 + 10025c: 4e 80 00 20 blr + +0000000000100260 : + 100260: 7c 63 1a 78 xor r3,r3,r3 + 100264: 7c 63 18 f8 not r3,r3 + 100268: 30 63 00 01 addic r3,r3,1 + 10026c: 7c 64 29 15 adde. r3,r4,r5 + 100270: 7d 60 00 26 mfcr r11 + 100274: 7c c0 01 15 adde. r6,r0,r0 + 100278: 7d 80 00 26 mfcr r12 + 10027c: 4e 80 00 20 blr + +0000000000100280 : + 100280: 38 80 ff ff li r4,-1 + 100284: 38 a0 00 00 li r5,0 + 100288: 7c 63 1a 78 xor r3,r3,r3 + 10028c: 7c 63 18 f8 not r3,r3 + 100290: 30 63 00 01 addic r3,r3,1 + 100294: 7c 64 29 15 adde. r3,r4,r5 + 100298: 7d 60 00 26 mfcr r11 + 10029c: 7c c0 01 15 adde. r6,r0,r0 + 1002a0: 7d 80 00 26 mfcr r12 + 1002a4: 4e 80 00 20 blr + +00000000001002a8 : + 1002a8: 7c 64 29 15 adde. r3,r4,r5 + 1002ac: 7d 60 00 26 mfcr r11 + 1002b0: 7c c0 01 15 adde. r6,r0,r0 + 1002b4: 7d 80 00 26 mfcr r12 + 1002b8: 4e 80 00 20 blr + +00000000001002bc : + 1002bc: 38 80 ff ff li r4,-1 + 1002c0: 38 a0 00 01 li r5,1 + 1002c4: 7c 64 29 15 adde. r3,r4,r5 + 1002c8: 7d 60 00 26 mfcr r11 + 1002cc: 7c c0 01 15 adde. r6,r0,r0 + 1002d0: 7d 80 00 26 mfcr r12 + 1002d4: 4e 80 00 20 blr + +00000000001002d8 : + 1002d8: 7c 63 1a 78 xor r3,r3,r3 + 1002dc: 7c 63 18 f8 not r3,r3 + 1002e0: 30 63 00 01 addic r3,r3,1 + 1002e4: 7c 64 29 15 adde. r3,r4,r5 + 1002e8: 7d 60 00 26 mfcr r11 + 1002ec: 7c c0 01 15 adde. r6,r0,r0 + 1002f0: 7d 80 00 26 mfcr r12 + 1002f4: 4e 80 00 20 blr + +00000000001002f8 : + 1002f8: 38 80 ff ff li r4,-1 + 1002fc: 38 a0 00 01 li r5,1 + 100300: 7c 63 1a 78 xor r3,r3,r3 + 100304: 7c 63 18 f8 not r3,r3 + 100308: 30 63 00 01 addic r3,r3,1 + 10030c: 7c 64 29 15 adde. r3,r4,r5 + 100310: 7d 60 00 26 mfcr r11 + 100314: 7c c0 01 15 adde. r6,r0,r0 + 100318: 7d 80 00 26 mfcr r12 + 10031c: 4e 80 00 20 blr + +0000000000100320 : + 100320: 7c 64 29 15 adde. r3,r4,r5 + 100324: 7d 60 00 26 mfcr r11 + 100328: 7c c0 01 15 adde. r6,r0,r0 + 10032c: 7d 80 00 26 mfcr r12 + 100330: 4e 80 00 20 blr + +0000000000100334 : + 100334: 38 80 ff ff li r4,-1 + 100338: 38 a0 00 7b li r5,123 + 10033c: 7c 64 29 15 adde. r3,r4,r5 + 100340: 7d 60 00 26 mfcr r11 + 100344: 7c c0 01 15 adde. r6,r0,r0 + 100348: 7d 80 00 26 mfcr r12 + 10034c: 4e 80 00 20 blr + +0000000000100350 : + 100350: 7c 63 1a 78 xor r3,r3,r3 + 100354: 7c 63 18 f8 not r3,r3 + 100358: 30 63 00 01 addic r3,r3,1 + 10035c: 7c 64 29 15 adde. r3,r4,r5 + 100360: 7d 60 00 26 mfcr r11 + 100364: 7c c0 01 15 adde. r6,r0,r0 + 100368: 7d 80 00 26 mfcr r12 + 10036c: 4e 80 00 20 blr + +0000000000100370 : + 100370: 38 80 ff ff li r4,-1 + 100374: 38 a0 00 7b li r5,123 + 100378: 7c 63 1a 78 xor r3,r3,r3 + 10037c: 7c 63 18 f8 not r3,r3 + 100380: 30 63 00 01 addic r3,r3,1 + 100384: 7c 64 29 15 adde. r3,r4,r5 + 100388: 7d 60 00 26 mfcr r11 + 10038c: 7c c0 01 15 adde. r6,r0,r0 + 100390: 7d 80 00 26 mfcr r12 + 100394: 4e 80 00 20 blr + +0000000000100398 : + 100398: 7c 64 29 15 adde. r3,r4,r5 + 10039c: 7d 60 00 26 mfcr r11 + 1003a0: 7c c0 01 15 adde. r6,r0,r0 + 1003a4: 7d 80 00 26 mfcr r12 + 1003a8: 4e 80 00 20 blr + +00000000001003ac : + 1003ac: 38 a0 ff ff li r5,-1 + 1003b0: 78 a4 f8 42 rldicl r4,r5,63,1 + 1003b4: 7c 64 29 15 adde. r3,r4,r5 + 1003b8: 7d 60 00 26 mfcr r11 + 1003bc: 7c c0 01 15 adde. r6,r0,r0 + 1003c0: 7d 80 00 26 mfcr r12 + 1003c4: 4e 80 00 20 blr + +00000000001003c8 : + 1003c8: 7c 63 1a 78 xor r3,r3,r3 + 1003cc: 7c 63 18 f8 not r3,r3 + 1003d0: 30 63 00 01 addic r3,r3,1 + 1003d4: 7c 64 29 15 adde. r3,r4,r5 + 1003d8: 7d 60 00 26 mfcr r11 + 1003dc: 7c c0 01 15 adde. r6,r0,r0 + 1003e0: 7d 80 00 26 mfcr r12 + 1003e4: 4e 80 00 20 blr + +00000000001003e8 : + 1003e8: 38 a0 ff ff li r5,-1 + 1003ec: 78 a4 f8 42 rldicl r4,r5,63,1 + 1003f0: 7c 63 1a 78 xor r3,r3,r3 + 1003f4: 7c 63 18 f8 not r3,r3 + 1003f8: 30 63 00 01 addic r3,r3,1 + 1003fc: 7c 64 29 15 adde. r3,r4,r5 + 100400: 7d 60 00 26 mfcr r11 + 100404: 7c c0 01 15 adde. r6,r0,r0 + 100408: 7d 80 00 26 mfcr r12 + 10040c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_adde.map b/src/xenia/cpu/frontend/test/bin/instr_adde.map index a48a1116d..d8725a623 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_adde.map +++ b/src/xenia/cpu/frontend/test/bin/instr_adde.map @@ -18,3 +18,23 @@ 000000000000016c t test_adde_9_constant 0000000000000180 t test_adde_10 0000000000000198 t test_adde_10_constant +00000000000001b8 t test_adde_cr_1 +00000000000001cc t test_adde_cr_1_constant +00000000000001e8 t test_adde_cr_2 +0000000000000208 t test_adde_cr_2_constant +0000000000000230 t test_adde_cr_3 +0000000000000244 t test_adde_cr_3_constant +0000000000000260 t test_adde_cr_4 +0000000000000280 t test_adde_cr_4_constant +00000000000002a8 t test_adde_cr_5 +00000000000002bc t test_adde_cr_5_constant +00000000000002d8 t test_adde_cr_6 +00000000000002f8 t test_adde_cr_6_constant +0000000000000320 t test_adde_cr_7 +0000000000000334 t test_adde_cr_7_constant +0000000000000350 t test_adde_cr_8 +0000000000000370 t test_adde_cr_8_constant +0000000000000398 t test_adde_cr_9 +00000000000003ac t test_adde_cr_9_constant +00000000000003c8 t test_adde_cr_10 +00000000000003e8 t test_adde_cr_10_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_addic.bin b/src/xenia/cpu/frontend/test/bin/instr_addic.bin index b7154c4b9b9cb188cedccbba41618c2b5dacce82..905d392a0f7aae4bbfcaea00053d2251d68ac19e 100644 GIT binary patch literal 128 zcmXqLVPLE|z$oI^z@T8!z`$sL#7AaZH2nXM%r}9mt8HLVgXu*VL+69cKo: - 10000c: 30 84 00 01 addic r4,r4,1 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 30 84 00 01 addic r4,r4,1 + 100014: 7c c0 01 14 adde r6,r0,r0 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 30 84 00 01 addic r4,r4,1 + 100020: 7c c0 01 14 adde r6,r0,r0 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 38 80 ff ff li r4,-1 + 10002c: 30 84 00 01 addic r4,r4,1 + 100030: 7c c0 01 14 adde r6,r0,r0 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 34 84 00 01 addic. r4,r4,1 + 10003c: 7c c0 01 14 adde r6,r0,r0 + 100040: 7d 80 00 26 mfcr r12 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 38 80 00 01 li r4,1 + 10004c: 34 84 00 01 addic. r4,r4,1 + 100050: 7c c0 01 14 adde r6,r0,r0 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 34 84 00 01 addic. r4,r4,1 + 100060: 7c c0 01 14 adde r6,r0,r0 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 ff ff li r4,-1 + 100070: 34 84 00 01 addic. r4,r4,1 + 100074: 7c c0 01 14 adde r6,r0,r0 + 100078: 7d 80 00 26 mfcr r12 + 10007c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addic.map b/src/xenia/cpu/frontend/test/bin/instr_addic.map index de7ccdb31..488a3185f 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addic.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addic.map @@ -1,2 +1,8 @@ 0000000000000000 t test_addic_1 -000000000000000c t test_addic_2 +000000000000000c t test_addic_1_constant +000000000000001c t test_addic_2 +0000000000000028 t test_addic_2_constant +0000000000000038 t test_addic_cr_1 +0000000000000048 t test_addic_cr_1_constant +000000000000005c t test_addic_cr_2 +000000000000006c t test_addic_cr_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_addis.bin b/src/xenia/cpu/frontend/test/bin/instr_addis.bin new file mode 100644 index 0000000000000000000000000000000000000000..1bff48598063e4f7553d9807c08d150bdbf542fe GIT binary patch literal 112 zcmcCXU|{rXU{J7NV7X+`z`$q&<=dn{#T$U)3xMKKK1?2@9>%sw`2Qbf28?Z!0u_Vn GhwuRn%^)NI literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_addis.dis b/src/xenia/cpu/frontend/test/bin/instr_addis.dis new file mode 100644 index 000000000..374a527b8 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_addis.dis @@ -0,0 +1,49 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 3c 60 00 01 lis r3,1 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 00 04 d2 li r0,1234 + 10000c: 38 80 00 01 li r4,1 + 100010: 3c 60 00 01 lis r3,1 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 3c 64 00 01 addis r3,r4,1 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 38 80 04 d2 li r4,1234 + 100024: 38 a0 00 01 li r5,1 + 100028: 3c 64 00 01 addis r3,r4,1 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 3c 60 00 01 lis r3,1 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 00 04 d2 li r0,1234 + 10003c: 3c 60 00 01 lis r3,1 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 3c 60 ff ff lis r3,-1 + 100048: 4e 80 00 20 blr + +000000000010004c : + 10004c: 38 00 04 d2 li r0,1234 + 100050: 3c 60 ff ff lis r3,-1 + 100054: 4e 80 00 20 blr + +0000000000100058 : + 100058: 3c 64 ff ff addis r3,r4,-1 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 38 80 04 d2 li r4,1234 + 100064: 38 a0 00 01 li r5,1 + 100068: 3c 64 ff ff addis r3,r4,-1 + 10006c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addis.map b/src/xenia/cpu/frontend/test/bin/instr_addis.map new file mode 100644 index 000000000..fce587749 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_addis.map @@ -0,0 +1,10 @@ +0000000000000000 t test_addis_1 +0000000000000008 t test_addis_1_constant +0000000000000018 t test_addis_2 +0000000000000020 t test_addis_2_constant +0000000000000030 t test_lis_1 +0000000000000038 t test_lis_1_constant +0000000000000044 t test_lis_2 +000000000000004c t test_lis_2_constant +0000000000000058 t test_subis_1 +0000000000000060 t test_subis_1_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.bin b/src/xenia/cpu/frontend/test/bin/instr_addme.bin index d89bee67a9108f42a5612d7bcb19b801607bb533..b94b5999cf4f68a8ec25c96e2e598aa3e0d9f26d 100644 GIT binary patch literal 704 zcmbc}RZ){H@xve)RUE7iha9qgpgJC8J|6RUaLFO- zw`lnPADNF!4_F;>?qeX%JO&0_b^-NY1%+R21A`h;7@~-w=|z#l5|$|PSj-27DXJP& kzoN*2;{cC5x>?XLMll1w`+;#nlKH@}B+dQkVUOZA0LotDtpET3 delta 7 OcmX@WdVpzz10w(nz5;mw diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.dis b/src/xenia/cpu/frontend/test/bin/instr_addme.dis index ee07c5821..3bdcf1920 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addme.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_addme.dis @@ -111,3 +111,131 @@ Disassembly of section .text: 100134: 7c 64 01 d4 addme r3,r4 100138: 7c c0 01 14 adde r6,r0,r0 10013c: 4e 80 00 20 blr + +0000000000100140 : + 100140: 7c 64 01 d5 addme. r3,r4 + 100144: 7c c0 01 14 adde r6,r0,r0 + 100148: 7d 80 00 26 mfcr r12 + 10014c: 4e 80 00 20 blr + +0000000000100150 : + 100150: 38 80 00 01 li r4,1 + 100154: 7c 64 01 d5 addme. r3,r4 + 100158: 7c c0 01 14 adde r6,r0,r0 + 10015c: 7d 80 00 26 mfcr r12 + 100160: 4e 80 00 20 blr + +0000000000100164 : + 100164: 7c 63 1a 78 xor r3,r3,r3 + 100168: 7c 63 18 f8 not r3,r3 + 10016c: 30 63 00 01 addic r3,r3,1 + 100170: 7c 64 01 d5 addme. r3,r4 + 100174: 7c c0 01 14 adde r6,r0,r0 + 100178: 7d 80 00 26 mfcr r12 + 10017c: 4e 80 00 20 blr + +0000000000100180 : + 100180: 38 80 00 01 li r4,1 + 100184: 7c 63 1a 78 xor r3,r3,r3 + 100188: 7c 63 18 f8 not r3,r3 + 10018c: 30 63 00 01 addic r3,r3,1 + 100190: 7c 64 01 d5 addme. r3,r4 + 100194: 7c c0 01 14 adde r6,r0,r0 + 100198: 7d 80 00 26 mfcr r12 + 10019c: 4e 80 00 20 blr + +00000000001001a0 : + 1001a0: 7c 64 01 d5 addme. r3,r4 + 1001a4: 7c c0 01 14 adde r6,r0,r0 + 1001a8: 7d 80 00 26 mfcr r12 + 1001ac: 4e 80 00 20 blr + +00000000001001b0 : + 1001b0: 38 80 00 0c li r4,12 + 1001b4: 7c 64 01 d5 addme. r3,r4 + 1001b8: 7c c0 01 14 adde r6,r0,r0 + 1001bc: 7d 80 00 26 mfcr r12 + 1001c0: 4e 80 00 20 blr + +00000000001001c4 : + 1001c4: 7c 63 1a 78 xor r3,r3,r3 + 1001c8: 7c 63 18 f8 not r3,r3 + 1001cc: 30 63 00 01 addic r3,r3,1 + 1001d0: 7c 64 01 d5 addme. r3,r4 + 1001d4: 7c c0 01 14 adde r6,r0,r0 + 1001d8: 7d 80 00 26 mfcr r12 + 1001dc: 4e 80 00 20 blr + +00000000001001e0 : + 1001e0: 38 80 00 0c li r4,12 + 1001e4: 7c 63 1a 78 xor r3,r3,r3 + 1001e8: 7c 63 18 f8 not r3,r3 + 1001ec: 30 63 00 01 addic r3,r3,1 + 1001f0: 7c 64 01 d5 addme. r3,r4 + 1001f4: 7c c0 01 14 adde r6,r0,r0 + 1001f8: 7d 80 00 26 mfcr r12 + 1001fc: 4e 80 00 20 blr + +0000000000100200 : + 100200: 7c 64 01 d5 addme. r3,r4 + 100204: 7c c0 01 14 adde r6,r0,r0 + 100208: 7d 80 00 26 mfcr r12 + 10020c: 4e 80 00 20 blr + +0000000000100210 : + 100210: 38 80 ff ff li r4,-1 + 100214: 7c 64 01 d5 addme. r3,r4 + 100218: 7c c0 01 14 adde r6,r0,r0 + 10021c: 7d 80 00 26 mfcr r12 + 100220: 4e 80 00 20 blr + +0000000000100224 : + 100224: 7c 63 1a 78 xor r3,r3,r3 + 100228: 7c 63 18 f8 not r3,r3 + 10022c: 30 63 00 01 addic r3,r3,1 + 100230: 7c 64 01 d5 addme. r3,r4 + 100234: 7c c0 01 14 adde r6,r0,r0 + 100238: 7d 80 00 26 mfcr r12 + 10023c: 4e 80 00 20 blr + +0000000000100240 : + 100240: 38 80 ff ff li r4,-1 + 100244: 7c 63 1a 78 xor r3,r3,r3 + 100248: 7c 63 18 f8 not r3,r3 + 10024c: 30 63 00 01 addic r3,r3,1 + 100250: 7c 64 01 d5 addme. r3,r4 + 100254: 7c c0 01 14 adde r6,r0,r0 + 100258: 7d 80 00 26 mfcr r12 + 10025c: 4e 80 00 20 blr + +0000000000100260 : + 100260: 7c 64 01 d5 addme. r3,r4 + 100264: 7c c0 01 14 adde r6,r0,r0 + 100268: 7d 80 00 26 mfcr r12 + 10026c: 4e 80 00 20 blr + +0000000000100270 : + 100270: 38 80 00 00 li r4,0 + 100274: 7c 64 01 d5 addme. r3,r4 + 100278: 7c c0 01 14 adde r6,r0,r0 + 10027c: 7d 80 00 26 mfcr r12 + 100280: 4e 80 00 20 blr + +0000000000100284 : + 100284: 7c 63 1a 78 xor r3,r3,r3 + 100288: 7c 63 18 f8 not r3,r3 + 10028c: 30 63 00 01 addic r3,r3,1 + 100290: 7c 64 01 d5 addme. r3,r4 + 100294: 7c c0 01 14 adde r6,r0,r0 + 100298: 7d 80 00 26 mfcr r12 + 10029c: 4e 80 00 20 blr + +00000000001002a0 : + 1002a0: 38 80 00 00 li r4,0 + 1002a4: 7c 63 1a 78 xor r3,r3,r3 + 1002a8: 7c 63 18 f8 not r3,r3 + 1002ac: 30 63 00 01 addic r3,r3,1 + 1002b0: 7c 64 01 d5 addme. r3,r4 + 1002b4: 7c c0 01 14 adde r6,r0,r0 + 1002b8: 7d 80 00 26 mfcr r12 + 1002bc: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.map b/src/xenia/cpu/frontend/test/bin/instr_addme.map index dbc64cb90..a06ea1ffb 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addme.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addme.map @@ -14,3 +14,19 @@ 00000000000000fc t test_addme_7_constant 000000000000010c t test_addme_8 0000000000000124 t test_addme_8_constant +0000000000000140 t test_addme_cr_1 +0000000000000150 t test_addme_cr_1_constant +0000000000000164 t test_addme_cr_2 +0000000000000180 t test_addme_cr_2_constant +00000000000001a0 t test_addme_cr_3 +00000000000001b0 t test_addme_cr_3_constant +00000000000001c4 t test_addme_cr_4 +00000000000001e0 t test_addme_cr_4_constant +0000000000000200 t test_addme_cr_5 +0000000000000210 t test_addme_cr_5_constant +0000000000000224 t test_addme_cr_6 +0000000000000240 t test_addme_cr_6_constant +0000000000000260 t test_addme_cr_7 +0000000000000270 t test_addme_cr_7_constant +0000000000000284 t test_addme_cr_8 +00000000000002a0 t test_addme_cr_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.bin b/src/xenia/cpu/frontend/test/bin/instr_addze.bin index da738d2d6228bcf803ce25d40690b74c3dc1462d..9c4fa9636f44597fecdf1a306b53851235f7ff36 100644 GIT binary patch literal 704 zcmbc}RZ){H@xve)RUE7iha9qgpgJC8J|6RUaLFO- zw`lnPADNF!4_F;>?qeX%JO&0_b^-NI1%+R21A`h;7@~-w=|z#l5|$|PSj-27DXJP& kzoN*2;{cC5x>?XLMll1w`+;#nlKH@}B+dQkVUOZA01>&{tpET3 delta 7 OcmX@WdVpzz10w(nz5;mw diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.dis b/src/xenia/cpu/frontend/test/bin/instr_addze.dis index 40472a41d..344674325 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addze.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_addze.dis @@ -111,3 +111,131 @@ Disassembly of section .text: 100134: 7c 64 01 94 addze r3,r4 100138: 7c c0 01 14 adde r6,r0,r0 10013c: 4e 80 00 20 blr + +0000000000100140 : + 100140: 7c 64 01 95 addze. r3,r4 + 100144: 7c c0 01 14 adde r6,r0,r0 + 100148: 7d 80 00 26 mfcr r12 + 10014c: 4e 80 00 20 blr + +0000000000100150 : + 100150: 38 80 00 01 li r4,1 + 100154: 7c 64 01 95 addze. r3,r4 + 100158: 7c c0 01 14 adde r6,r0,r0 + 10015c: 7d 80 00 26 mfcr r12 + 100160: 4e 80 00 20 blr + +0000000000100164 : + 100164: 7c 63 1a 78 xor r3,r3,r3 + 100168: 7c 63 18 f8 not r3,r3 + 10016c: 30 63 00 01 addic r3,r3,1 + 100170: 7c 64 01 95 addze. r3,r4 + 100174: 7c c0 01 14 adde r6,r0,r0 + 100178: 7d 80 00 26 mfcr r12 + 10017c: 4e 80 00 20 blr + +0000000000100180 : + 100180: 38 80 00 01 li r4,1 + 100184: 7c 63 1a 78 xor r3,r3,r3 + 100188: 7c 63 18 f8 not r3,r3 + 10018c: 30 63 00 01 addic r3,r3,1 + 100190: 7c 64 01 95 addze. r3,r4 + 100194: 7c c0 01 14 adde r6,r0,r0 + 100198: 7d 80 00 26 mfcr r12 + 10019c: 4e 80 00 20 blr + +00000000001001a0 : + 1001a0: 7c 64 01 95 addze. r3,r4 + 1001a4: 7c c0 01 14 adde r6,r0,r0 + 1001a8: 7d 80 00 26 mfcr r12 + 1001ac: 4e 80 00 20 blr + +00000000001001b0 : + 1001b0: 38 80 00 0c li r4,12 + 1001b4: 7c 64 01 95 addze. r3,r4 + 1001b8: 7c c0 01 14 adde r6,r0,r0 + 1001bc: 7d 80 00 26 mfcr r12 + 1001c0: 4e 80 00 20 blr + +00000000001001c4 : + 1001c4: 7c 63 1a 78 xor r3,r3,r3 + 1001c8: 7c 63 18 f8 not r3,r3 + 1001cc: 30 63 00 01 addic r3,r3,1 + 1001d0: 7c 64 01 95 addze. r3,r4 + 1001d4: 7c c0 01 14 adde r6,r0,r0 + 1001d8: 7d 80 00 26 mfcr r12 + 1001dc: 4e 80 00 20 blr + +00000000001001e0 : + 1001e0: 38 80 00 0c li r4,12 + 1001e4: 7c 63 1a 78 xor r3,r3,r3 + 1001e8: 7c 63 18 f8 not r3,r3 + 1001ec: 30 63 00 01 addic r3,r3,1 + 1001f0: 7c 64 01 95 addze. r3,r4 + 1001f4: 7c c0 01 14 adde r6,r0,r0 + 1001f8: 7d 80 00 26 mfcr r12 + 1001fc: 4e 80 00 20 blr + +0000000000100200 : + 100200: 7c 64 01 95 addze. r3,r4 + 100204: 7c c0 01 14 adde r6,r0,r0 + 100208: 7d 80 00 26 mfcr r12 + 10020c: 4e 80 00 20 blr + +0000000000100210 : + 100210: 38 80 ff ff li r4,-1 + 100214: 7c 64 01 95 addze. r3,r4 + 100218: 7c c0 01 14 adde r6,r0,r0 + 10021c: 7d 80 00 26 mfcr r12 + 100220: 4e 80 00 20 blr + +0000000000100224 : + 100224: 7c 63 1a 78 xor r3,r3,r3 + 100228: 7c 63 18 f8 not r3,r3 + 10022c: 30 63 00 01 addic r3,r3,1 + 100230: 7c 64 01 95 addze. r3,r4 + 100234: 7c c0 01 14 adde r6,r0,r0 + 100238: 7d 80 00 26 mfcr r12 + 10023c: 4e 80 00 20 blr + +0000000000100240 : + 100240: 38 80 ff ff li r4,-1 + 100244: 7c 63 1a 78 xor r3,r3,r3 + 100248: 7c 63 18 f8 not r3,r3 + 10024c: 30 63 00 01 addic r3,r3,1 + 100250: 7c 64 01 95 addze. r3,r4 + 100254: 7c c0 01 14 adde r6,r0,r0 + 100258: 7d 80 00 26 mfcr r12 + 10025c: 4e 80 00 20 blr + +0000000000100260 : + 100260: 7c 64 01 95 addze. r3,r4 + 100264: 7c c0 01 14 adde r6,r0,r0 + 100268: 7d 80 00 26 mfcr r12 + 10026c: 4e 80 00 20 blr + +0000000000100270 : + 100270: 38 80 00 00 li r4,0 + 100274: 7c 64 01 95 addze. r3,r4 + 100278: 7c c0 01 14 adde r6,r0,r0 + 10027c: 7d 80 00 26 mfcr r12 + 100280: 4e 80 00 20 blr + +0000000000100284 : + 100284: 7c 63 1a 78 xor r3,r3,r3 + 100288: 7c 63 18 f8 not r3,r3 + 10028c: 30 63 00 01 addic r3,r3,1 + 100290: 7c 64 01 95 addze. r3,r4 + 100294: 7c c0 01 14 adde r6,r0,r0 + 100298: 7d 80 00 26 mfcr r12 + 10029c: 4e 80 00 20 blr + +00000000001002a0 : + 1002a0: 38 80 00 00 li r4,0 + 1002a4: 7c 63 1a 78 xor r3,r3,r3 + 1002a8: 7c 63 18 f8 not r3,r3 + 1002ac: 30 63 00 01 addic r3,r3,1 + 1002b0: 7c 64 01 95 addze. r3,r4 + 1002b4: 7c c0 01 14 adde r6,r0,r0 + 1002b8: 7d 80 00 26 mfcr r12 + 1002bc: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.map b/src/xenia/cpu/frontend/test/bin/instr_addze.map index 8c4cc6597..b79fc25cf 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addze.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addze.map @@ -14,3 +14,19 @@ 00000000000000fc t test_addze_7_constant 000000000000010c t test_addze_8 0000000000000124 t test_addze_8_constant +0000000000000140 t test_addze_cr_1 +0000000000000150 t test_addze_cr_1_constant +0000000000000164 t test_addze_cr_2 +0000000000000180 t test_addze_cr_2_constant +00000000000001a0 t test_addze_cr_3 +00000000000001b0 t test_addze_cr_3_constant +00000000000001c4 t test_addze_cr_4 +00000000000001e0 t test_addze_cr_4_constant +0000000000000200 t test_addze_cr_5 +0000000000000210 t test_addze_cr_5_constant +0000000000000224 t test_addze_cr_6 +0000000000000240 t test_addze_cr_6_constant +0000000000000260 t test_addze_cr_7 +0000000000000270 t test_addze_cr_7_constant +0000000000000284 t test_addze_cr_8 +00000000000002a0 t test_addze_cr_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_and.bin b/src/xenia/cpu/frontend/test/bin/instr_and.bin new file mode 100644 index 0000000000000000000000000000000000000000..8456a48cf3a821122b6e76ba7e05df994c7cf408 GIT binary patch literal 304 zcmb08lBF?}7A#QVZ literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_and.dis b/src/xenia/cpu/frontend/test/bin/instr_and.dis new file mode 100644 index 000000000..915dd9d97 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_and.dis @@ -0,0 +1,117 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c ab c8 38 and r11,r5,r25 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 a0 ff ff li r5,-1 + 10000c: 3b 20 ff ff li r25,-1 + 100010: 7c ab c8 38 and r11,r5,r25 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c ab c8 38 and r11,r5,r25 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 38 a0 ff ff li r5,-1 + 100024: 3b 20 00 00 li r25,0 + 100028: 7c ab c8 38 and r11,r5,r25 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c ab c8 38 and r11,r5,r25 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 a0 00 00 li r5,0 + 10003c: 3b 20 ff ff li r25,-1 + 100040: 7c ab c8 38 and r11,r5,r25 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c ab c8 38 and r11,r5,r25 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 a0 ff ff li r5,-1 + 100054: 3b 20 ff ff li r25,-1 + 100058: 7b 39 04 20 clrldi r25,r25,48 + 10005c: 7c ab c8 38 and r11,r5,r25 + 100060: 4e 80 00 20 blr + +0000000000100064 : + 100064: 7c 0b c8 38 and r11,r0,r25 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 3c 00 10 00 lis r0,4096 + 100070: 60 00 00 ff ori r0,r0,255 + 100074: 3b 20 ff ff li r25,-1 + 100078: 7b 39 04 20 clrldi r25,r25,48 + 10007c: 7c 0b c8 38 and r11,r0,r25 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 7c ab c8 39 and. r11,r5,r25 + 100088: 7d 80 00 26 mfcr r12 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 38 a0 ff ff li r5,-1 + 100094: 3b 20 ff ff li r25,-1 + 100098: 7c ab c8 39 and. r11,r5,r25 + 10009c: 7d 80 00 26 mfcr r12 + 1000a0: 4e 80 00 20 blr + +00000000001000a4 : + 1000a4: 7c ab c8 39 and. r11,r5,r25 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 a0 ff ff li r5,-1 + 1000b4: 3b 20 00 00 li r25,0 + 1000b8: 7c ab c8 39 and. r11,r5,r25 + 1000bc: 7d 80 00 26 mfcr r12 + 1000c0: 4e 80 00 20 blr + +00000000001000c4 : + 1000c4: 7c ab c8 39 and. r11,r5,r25 + 1000c8: 7d 80 00 26 mfcr r12 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 38 a0 00 00 li r5,0 + 1000d4: 3b 20 ff ff li r25,-1 + 1000d8: 7c ab c8 39 and. r11,r5,r25 + 1000dc: 7d 80 00 26 mfcr r12 + 1000e0: 4e 80 00 20 blr + +00000000001000e4 : + 1000e4: 7c ab c8 39 and. r11,r5,r25 + 1000e8: 7d 80 00 26 mfcr r12 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 38 a0 ff ff li r5,-1 + 1000f4: 3b 20 ff ff li r25,-1 + 1000f8: 7b 39 04 20 clrldi r25,r25,48 + 1000fc: 7c ab c8 39 and. r11,r5,r25 + 100100: 7d 80 00 26 mfcr r12 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 7c 0b c8 39 and. r11,r0,r25 + 10010c: 7d 80 00 26 mfcr r12 + 100110: 4e 80 00 20 blr + +0000000000100114 : + 100114: 3c 00 10 00 lis r0,4096 + 100118: 60 00 00 ff ori r0,r0,255 + 10011c: 3b 20 ff ff li r25,-1 + 100120: 7b 39 04 20 clrldi r25,r25,48 + 100124: 7c 0b c8 39 and. r11,r0,r25 + 100128: 7d 80 00 26 mfcr r12 + 10012c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_and.map b/src/xenia/cpu/frontend/test/bin/instr_and.map new file mode 100644 index 000000000..fd4e6ef37 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_and.map @@ -0,0 +1,20 @@ +0000000000000000 t test_and_1 +0000000000000008 t test_and_1_constant +0000000000000018 t test_and_2 +0000000000000020 t test_and_2_constant +0000000000000030 t test_and_3 +0000000000000038 t test_and_3_constant +0000000000000048 t test_and_4 +0000000000000050 t test_and_4_constant +0000000000000064 t test_and_5 +000000000000006c t test_and_5_constant +0000000000000084 t test_and_cr_1 +0000000000000090 t test_and_cr_1_constant +00000000000000a4 t test_and_cr_2 +00000000000000b0 t test_and_cr_2_constant +00000000000000c4 t test_and_cr_3 +00000000000000d0 t test_and_cr_3_constant +00000000000000e4 t test_and_cr_4 +00000000000000f0 t test_and_cr_4_constant +0000000000000108 t test_and_cr_5 +0000000000000114 t test_and_cr_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_andc.bin b/src/xenia/cpu/frontend/test/bin/instr_andc.bin new file mode 100644 index 0000000000000000000000000000000000000000..4d408ca41b28a6b4baed8501204e31d2a534192c GIT binary patch literal 304 zcmb08lBF?}7X`6U; literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_andc.dis b/src/xenia/cpu/frontend/test/bin/instr_andc.dis new file mode 100644 index 000000000..bec397567 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_andc.dis @@ -0,0 +1,117 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c ab c8 78 andc r11,r5,r25 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 a0 ff ff li r5,-1 + 10000c: 3b 20 ff ff li r25,-1 + 100010: 7c ab c8 78 andc r11,r5,r25 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c ab c8 78 andc r11,r5,r25 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 38 a0 ff ff li r5,-1 + 100024: 3b 20 00 00 li r25,0 + 100028: 7c ab c8 78 andc r11,r5,r25 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c ab c8 78 andc r11,r5,r25 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 a0 00 00 li r5,0 + 10003c: 3b 20 ff ff li r25,-1 + 100040: 7c ab c8 78 andc r11,r5,r25 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c ab c8 78 andc r11,r5,r25 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 a0 ff ff li r5,-1 + 100054: 3b 20 ff ff li r25,-1 + 100058: 7b 39 04 20 clrldi r25,r25,48 + 10005c: 7c ab c8 78 andc r11,r5,r25 + 100060: 4e 80 00 20 blr + +0000000000100064 : + 100064: 7c 0b c8 78 andc r11,r0,r25 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 3c 00 10 00 lis r0,4096 + 100070: 60 00 00 ff ori r0,r0,255 + 100074: 3b 20 ff ff li r25,-1 + 100078: 7b 39 04 20 clrldi r25,r25,48 + 10007c: 7c 0b c8 78 andc r11,r0,r25 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 7c ab c8 79 andc. r11,r5,r25 + 100088: 7d 80 00 26 mfcr r12 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 38 a0 ff ff li r5,-1 + 100094: 3b 20 ff ff li r25,-1 + 100098: 7c ab c8 79 andc. r11,r5,r25 + 10009c: 7d 80 00 26 mfcr r12 + 1000a0: 4e 80 00 20 blr + +00000000001000a4 : + 1000a4: 7c ab c8 79 andc. r11,r5,r25 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 a0 ff ff li r5,-1 + 1000b4: 3b 20 00 00 li r25,0 + 1000b8: 7c ab c8 79 andc. r11,r5,r25 + 1000bc: 7d 80 00 26 mfcr r12 + 1000c0: 4e 80 00 20 blr + +00000000001000c4 : + 1000c4: 7c ab c8 79 andc. r11,r5,r25 + 1000c8: 7d 80 00 26 mfcr r12 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 38 a0 00 00 li r5,0 + 1000d4: 3b 20 ff ff li r25,-1 + 1000d8: 7c ab c8 79 andc. r11,r5,r25 + 1000dc: 7d 80 00 26 mfcr r12 + 1000e0: 4e 80 00 20 blr + +00000000001000e4 : + 1000e4: 7c ab c8 79 andc. r11,r5,r25 + 1000e8: 7d 80 00 26 mfcr r12 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 38 a0 ff ff li r5,-1 + 1000f4: 3b 20 ff ff li r25,-1 + 1000f8: 7b 39 04 20 clrldi r25,r25,48 + 1000fc: 7c ab c8 79 andc. r11,r5,r25 + 100100: 7d 80 00 26 mfcr r12 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 7c 0b c8 79 andc. r11,r0,r25 + 10010c: 7d 80 00 26 mfcr r12 + 100110: 4e 80 00 20 blr + +0000000000100114 : + 100114: 3c 00 10 00 lis r0,4096 + 100118: 60 00 00 ff ori r0,r0,255 + 10011c: 3b 20 ff ff li r25,-1 + 100120: 7b 39 04 20 clrldi r25,r25,48 + 100124: 7c 0b c8 79 andc. r11,r0,r25 + 100128: 7d 80 00 26 mfcr r12 + 10012c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_andc.map b/src/xenia/cpu/frontend/test/bin/instr_andc.map new file mode 100644 index 000000000..d2766bacb --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_andc.map @@ -0,0 +1,20 @@ +0000000000000000 t test_andc_1 +0000000000000008 t test_andc_1_constant +0000000000000018 t test_andc_2 +0000000000000020 t test_andc_2_constant +0000000000000030 t test_andc_3 +0000000000000038 t test_andc_3_constant +0000000000000048 t test_andc_4 +0000000000000050 t test_andc_4_constant +0000000000000064 t test_andc_5 +000000000000006c t test_andc_5_constant +0000000000000084 t test_andc_cr_1 +0000000000000090 t test_andc_cr_1_constant +00000000000000a4 t test_andc_cr_2 +00000000000000b0 t test_andc_cr_2_constant +00000000000000c4 t test_andc_cr_3 +00000000000000d0 t test_andc_cr_3_constant +00000000000000e4 t test_andc_cr_4 +00000000000000f0 t test_andc_cr_4_constant +0000000000000108 t test_andc_cr_5 +0000000000000114 t test_andc_cr_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_andi.bin b/src/xenia/cpu/frontend/test/bin/instr_andi.bin new file mode 100644 index 0000000000000000000000000000000000000000..e00b961fd547189406b2b5019cbcd2f9bc067300 GIT binary patch literal 140 zcmXR|ed=Fr1B04h1A~Iag8%;ukoX0w85m%4sO literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_andi.dis b/src/xenia/cpu/frontend/test/bin/instr_andi.dis new file mode 100644 index 000000000..7649d50a5 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_andi.dis @@ -0,0 +1,56 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 70 ab ca fe andi. r11,r5,51966 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 a0 ff ff li r5,-1 + 100010: 70 ab ca fe andi. r11,r5,51966 + 100014: 7d 80 00 26 mfcr r12 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 70 ab 00 00 andi. r11,r5,0 + 100020: 7d 80 00 26 mfcr r12 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 70 ab 00 00 andi. r11,r5,0 + 10002c: 7d 80 00 26 mfcr r12 + 100030: 4e 80 00 20 blr + +0000000000100034 : + 100034: 70 ab ff ff andi. r11,r5,65535 + 100038: 7d 80 00 26 mfcr r12 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 38 a0 00 00 li r5,0 + 100044: 70 ab ff ff andi. r11,r5,65535 + 100048: 7d 80 00 26 mfcr r12 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 70 ab ca fe andi. r11,r5,51966 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 38 a0 ff ff li r5,-1 + 100060: 70 ab ca fe andi. r11,r5,51966 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 70 0b ff ff andi. r11,r0,65535 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 3c 00 10 00 lis r0,4096 + 10007c: 60 00 00 ff ori r0,r0,255 + 100080: 70 0b ff ff andi. r11,r0,65535 + 100084: 7d 80 00 26 mfcr r12 + 100088: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_andi.map b/src/xenia/cpu/frontend/test/bin/instr_andi.map new file mode 100644 index 000000000..ce419b1fb --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_andi.map @@ -0,0 +1,10 @@ +0000000000000000 t test_andi_cr_1 +000000000000000c t test_andi_cr_1_constant +000000000000001c t test_andi_cr_2 +0000000000000028 t test_andi_cr_2_constant +0000000000000034 t test_andi_cr_3 +0000000000000040 t test_andi_cr_3_constant +0000000000000050 t test_andi_cr_4 +000000000000005c t test_andi_cr_4_constant +000000000000006c t test_andi_cr_5 +0000000000000078 t test_andi_cr_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_andis.bin b/src/xenia/cpu/frontend/test/bin/instr_andis.bin new file mode 100644 index 0000000000000000000000000000000000000000..43152b45fabaff5df5857c97aefa46e5b66e6583 GIT binary patch literal 140 zcmXR}ed=Fr1B04h1A~Iag8%: + 100000: 74 ab ca fe andis. r11,r5,51966 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 a0 ff ff li r5,-1 + 100010: 74 ab ca fe andis. r11,r5,51966 + 100014: 7d 80 00 26 mfcr r12 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 74 ab 00 00 andis. r11,r5,0 + 100020: 7d 80 00 26 mfcr r12 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 74 ab 00 00 andis. r11,r5,0 + 10002c: 7d 80 00 26 mfcr r12 + 100030: 4e 80 00 20 blr + +0000000000100034 : + 100034: 74 ab ff ff andis. r11,r5,65535 + 100038: 7d 80 00 26 mfcr r12 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 38 a0 00 00 li r5,0 + 100044: 74 ab ff ff andis. r11,r5,65535 + 100048: 7d 80 00 26 mfcr r12 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 74 ab ca fe andis. r11,r5,51966 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 38 a0 ff ff li r5,-1 + 100060: 74 ab ca fe andis. r11,r5,51966 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 74 0b ff ff andis. r11,r0,65535 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 3c 00 10 00 lis r0,4096 + 10007c: 60 00 00 ff ori r0,r0,255 + 100080: 74 0b ff ff andis. r11,r0,65535 + 100084: 7d 80 00 26 mfcr r12 + 100088: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_andis.map b/src/xenia/cpu/frontend/test/bin/instr_andis.map new file mode 100644 index 000000000..f18d72140 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_andis.map @@ -0,0 +1,10 @@ +0000000000000000 t test_andis_cr_1 +000000000000000c t test_andis_cr_1_constant +000000000000001c t test_andis_cr_2 +0000000000000028 t test_andis_cr_2_constant +0000000000000034 t test_andis_cr_3 +0000000000000040 t test_andis_cr_3_constant +0000000000000050 t test_andis_cr_4 +000000000000005c t test_andis_cr_4_constant +000000000000006c t test_andis_cr_5 +0000000000000078 t test_andis_cr_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmp.bin b/src/xenia/cpu/frontend/test/bin/instr_cmp.bin new file mode 100644 index 0000000000000000000000000000000000000000..cda90b90fc197ec29f8ea1d39da32d95e80339b8 GIT binary patch literal 316 zcmbjNgSDN(EwD_0#wtCriK}ZIY{C)NNf~y zki=2c0Nn#r$Am0~%m%ub31kkk7&05#KNiVAwJoS>>zYyB46+MZtQJ)sY!|W^07Q9B AT>t<8 literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmp.dis b/src/xenia/cpu/frontend/test/bin/instr_cmp.dis new file mode 100644 index 000000000..06d570060 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmp.dis @@ -0,0 +1,116 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 23 20 00 cmpd r3,r4 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 60 00 01 li r3,1 + 100010: 78 63 07 c6 rldicr r3,r3,32,31 + 100014: 78 64 0f a4 rldicr r4,r3,1,62 + 100018: 7c 23 20 00 cmpd r3,r4 + 10001c: 7d 80 00 26 mfcr r12 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 23 20 00 cmpd r3,r4 + 100028: 7d 80 00 26 mfcr r12 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 38 80 00 01 li r4,1 + 100034: 78 84 07 c6 rldicr r4,r4,32,31 + 100038: 78 83 0f a4 rldicr r3,r4,1,62 + 10003c: 7c 23 20 00 cmpd r3,r4 + 100040: 7d 80 00 26 mfcr r12 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 03 20 00 cmpw r3,r4 + 10004c: 7d 80 00 26 mfcr r12 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 38 60 00 01 li r3,1 + 100058: 78 63 07 c6 rldicr r3,r3,32,31 + 10005c: 78 64 0f a4 rldicr r4,r3,1,62 + 100060: 7c 03 20 00 cmpw r3,r4 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 7c 03 20 00 cmpw r3,r4 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 38 80 00 01 li r4,1 + 10007c: 78 84 07 c6 rldicr r4,r4,32,31 + 100080: 78 83 0f a4 rldicr r3,r4,1,62 + 100084: 7c 03 20 00 cmpw r3,r4 + 100088: 7d 80 00 26 mfcr r12 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 03 20 00 cmpw r3,r4 + 100094: 7d 80 00 26 mfcr r12 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 38 60 00 01 li r3,1 + 1000a0: 38 80 00 02 li r4,2 + 1000a4: 7c 03 20 00 cmpw r3,r4 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 7c 03 20 00 cmpw r3,r4 + 1000b4: 7d 80 00 26 mfcr r12 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 38 60 00 02 li r3,2 + 1000c0: 38 80 00 01 li r4,1 + 1000c4: 7c 03 20 00 cmpw r3,r4 + 1000c8: 7d 80 00 26 mfcr r12 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 7c 03 20 00 cmpw r3,r4 + 1000d4: 7d 80 00 26 mfcr r12 + 1000d8: 4e 80 00 20 blr + +00000000001000dc : + 1000dc: 38 60 00 01 li r3,1 + 1000e0: 78 63 07 c6 rldicr r3,r3,32,31 + 1000e4: 78 64 0f a4 rldicr r4,r3,1,62 + 1000e8: 38 63 00 02 addi r3,r3,2 + 1000ec: 38 84 00 01 addi r4,r4,1 + 1000f0: 7c 03 20 00 cmpw r3,r4 + 1000f4: 7d 80 00 26 mfcr r12 + 1000f8: 4e 80 00 20 blr + +00000000001000fc : + 1000fc: 7e 83 20 00 cmpw cr5,r3,r4 + 100100: 7d 80 00 26 mfcr r12 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 38 60 00 01 li r3,1 + 10010c: 38 80 00 02 li r4,2 + 100110: 7e 83 20 00 cmpw cr5,r3,r4 + 100114: 7d 80 00 26 mfcr r12 + 100118: 4e 80 00 20 blr + +000000000010011c : + 10011c: 7d 83 20 00 cmpw cr3,r3,r4 + 100120: 7d 80 00 26 mfcr r12 + 100124: 4e 80 00 20 blr + +0000000000100128 : + 100128: 38 60 00 02 li r3,2 + 10012c: 38 80 00 01 li r4,1 + 100130: 7d 83 20 00 cmpw cr3,r3,r4 + 100134: 7d 80 00 26 mfcr r12 + 100138: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmp.map b/src/xenia/cpu/frontend/test/bin/instr_cmp.map new file mode 100644 index 000000000..3eb9d0a68 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmp.map @@ -0,0 +1,18 @@ +0000000000000000 t test_cmpd_1 +000000000000000c t test_cmpd_1_constant +0000000000000024 t test_cmpd_2 +0000000000000030 t test_cmpd_2_constant +0000000000000048 t test_cmpw_1 +0000000000000054 t test_cmpw_1_constant +000000000000006c t test_cmpw_2 +0000000000000078 t test_cmpw_2_constant +0000000000000090 t test_cmpw_3 +000000000000009c t test_cmpw_3_constant +00000000000000b0 t test_cmpw_4 +00000000000000bc t test_cmpw_4_constant +00000000000000d0 t test_cmpw_5 +00000000000000dc t test_cmpw_5_constant +00000000000000fc t test_cmp_1 +0000000000000108 t test_cmp_1_constant +000000000000011c t test_cmp_2 +0000000000000128 t test_cmp_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpi.bin b/src/xenia/cpu/frontend/test/bin/instr_cmpi.bin new file mode 100644 index 0000000000000000000000000000000000000000..085d37349a525b62c2b82b8ef7b49b2ff7f8e22f GIT binary patch literal 216 zcmdN: + 100000: 2c 23 00 02 cmpdi r3,2 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 60 00 01 li r3,1 + 100010: 78 63 07 c6 rldicr r3,r3,32,31 + 100014: 2c 23 00 02 cmpdi r3,2 + 100018: 7d 80 00 26 mfcr r12 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 2c 23 00 02 cmpdi r3,2 + 100024: 7d 80 00 26 mfcr r12 + 100028: 4e 80 00 20 blr + +000000000010002c : + 10002c: 38 60 00 01 li r3,1 + 100030: 2c 23 00 02 cmpdi r3,2 + 100034: 7d 80 00 26 mfcr r12 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 2c 03 00 02 cmpwi r3,2 + 100040: 7d 80 00 26 mfcr r12 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 38 60 00 01 li r3,1 + 10004c: 78 63 07 c6 rldicr r3,r3,32,31 + 100050: 2c 03 00 02 cmpwi r3,2 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 2c 03 00 01 cmpwi r3,1 + 100060: 7d 80 00 26 mfcr r12 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 60 00 02 li r3,2 + 10006c: 2c 03 00 01 cmpwi r3,1 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 2c 03 00 01 cmpwi r3,1 + 10007c: 7d 80 00 26 mfcr r12 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 38 60 00 01 li r3,1 + 100088: 78 63 07 c6 rldicr r3,r3,32,31 + 10008c: 78 64 0f a4 rldicr r4,r3,1,62 + 100090: 38 63 00 02 addi r3,r3,2 + 100094: 2c 03 00 01 cmpwi r3,1 + 100098: 7d 80 00 26 mfcr r12 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 2e 83 00 02 cmpwi cr5,r3,2 + 1000a4: 7d 80 00 26 mfcr r12 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 60 00 01 li r3,1 + 1000b0: 2e 83 00 02 cmpwi cr5,r3,2 + 1000b4: 7d 80 00 26 mfcr r12 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 2d 83 00 01 cmpwi cr3,r3,1 + 1000c0: 7d 80 00 26 mfcr r12 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 60 00 02 li r3,2 + 1000cc: 2d 83 00 01 cmpwi cr3,r3,1 + 1000d0: 7d 80 00 26 mfcr r12 + 1000d4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpi.map b/src/xenia/cpu/frontend/test/bin/instr_cmpi.map new file mode 100644 index 000000000..c0e141624 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmpi.map @@ -0,0 +1,14 @@ +0000000000000000 t test_cmpdi_1 +000000000000000c t test_cmpdi_1_constant +0000000000000020 t test_cmpdi_2 +000000000000002c t test_cmpdi_2_constant +000000000000003c t test_cmpwi_1 +0000000000000048 t test_cmpwi_1_constant +000000000000005c t test_cmpwi_2 +0000000000000068 t test_cmpwi_2_constant +0000000000000078 t test_cmpwi_5 +0000000000000084 t test_cmpwi_5_constant +00000000000000a0 t test_cmpi_1 +00000000000000ac t test_cmpi_1_constant +00000000000000bc t test_cmpi_2 +00000000000000c8 t test_cmpi_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpl.bin b/src/xenia/cpu/frontend/test/bin/instr_cmpl.bin new file mode 100644 index 0000000000000000000000000000000000000000..d6bc27de900b9f8ca0159f5298682c8af671db9e GIT binary patch literal 360 zcmbjNgSDN(EwD_0#wtCriK}ZIY{C)NNf~y zki=2c0Nn#r$Am0~%m%ub31kkk7&05#KNiVAwJo^S+9cHfPe}g%zb0AY2gGeZRFKW8 UYew}S$X&={wW#u7cOi=b0F^;uSO5S3 literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpl.dis b/src/xenia/cpu/frontend/test/bin/instr_cmpl.dis new file mode 100644 index 000000000..35ebe39a8 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmpl.dis @@ -0,0 +1,131 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 23 20 40 cmpld r3,r4 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 60 00 01 li r3,1 + 100010: 78 63 07 c6 rldicr r3,r3,32,31 + 100014: 78 64 0f a4 rldicr r4,r3,1,62 + 100018: 7c 23 20 40 cmpld r3,r4 + 10001c: 7d 80 00 26 mfcr r12 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 23 20 40 cmpld r3,r4 + 100028: 7d 80 00 26 mfcr r12 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 38 80 00 01 li r4,1 + 100034: 78 84 07 c6 rldicr r4,r4,32,31 + 100038: 78 83 0f a4 rldicr r3,r4,1,62 + 10003c: 7c 23 20 40 cmpld r3,r4 + 100040: 7d 80 00 26 mfcr r12 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 03 20 40 cmplw r3,r4 + 10004c: 7d 80 00 26 mfcr r12 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 38 60 00 01 li r3,1 + 100058: 78 63 07 c6 rldicr r3,r3,32,31 + 10005c: 78 64 0f a4 rldicr r4,r3,1,62 + 100060: 7c 03 20 40 cmplw r3,r4 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 7c 03 20 40 cmplw r3,r4 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 38 80 00 01 li r4,1 + 10007c: 78 84 07 c6 rldicr r4,r4,32,31 + 100080: 78 83 0f a4 rldicr r3,r4,1,62 + 100084: 7c 03 20 40 cmplw r3,r4 + 100088: 7d 80 00 26 mfcr r12 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 03 20 40 cmplw r3,r4 + 100094: 7d 80 00 26 mfcr r12 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 38 60 00 01 li r3,1 + 1000a0: 38 80 00 02 li r4,2 + 1000a4: 7c 03 20 40 cmplw r3,r4 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 7c 03 20 40 cmplw r3,r4 + 1000b4: 7d 80 00 26 mfcr r12 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 38 60 00 02 li r3,2 + 1000c0: 38 80 00 01 li r4,1 + 1000c4: 7c 03 20 40 cmplw r3,r4 + 1000c8: 7d 80 00 26 mfcr r12 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 7c 03 20 40 cmplw r3,r4 + 1000d4: 7d 80 00 26 mfcr r12 + 1000d8: 4e 80 00 20 blr + +00000000001000dc : + 1000dc: 38 60 00 01 li r3,1 + 1000e0: 78 63 07 c6 rldicr r3,r3,32,31 + 1000e4: 78 64 0f a4 rldicr r4,r3,1,62 + 1000e8: 38 63 00 02 addi r3,r3,2 + 1000ec: 38 84 00 01 addi r4,r4,1 + 1000f0: 7c 03 20 40 cmplw r3,r4 + 1000f4: 7d 80 00 26 mfcr r12 + 1000f8: 4e 80 00 20 blr + +00000000001000fc : + 1000fc: 7c 03 20 40 cmplw r3,r4 + 100100: 7d 80 00 26 mfcr r12 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 3c 60 7f ff lis r3,32767 + 10010c: 60 63 ff ff ori r3,r3,65535 + 100110: 7c 63 18 f8 not r3,r3 + 100114: 38 80 00 01 li r4,1 + 100118: 78 84 f8 24 rldicr r4,r4,31,32 + 10011c: 7c 03 20 40 cmplw r3,r4 + 100120: 7d 80 00 26 mfcr r12 + 100124: 4e 80 00 20 blr + +0000000000100128 : + 100128: 7e 83 20 40 cmplw cr5,r3,r4 + 10012c: 7d 80 00 26 mfcr r12 + 100130: 4e 80 00 20 blr + +0000000000100134 : + 100134: 38 60 00 01 li r3,1 + 100138: 38 80 00 02 li r4,2 + 10013c: 7e 83 20 40 cmplw cr5,r3,r4 + 100140: 7d 80 00 26 mfcr r12 + 100144: 4e 80 00 20 blr + +0000000000100148 : + 100148: 7d 83 20 40 cmplw cr3,r3,r4 + 10014c: 7d 80 00 26 mfcr r12 + 100150: 4e 80 00 20 blr + +0000000000100154 : + 100154: 38 60 00 02 li r3,2 + 100158: 38 80 00 01 li r4,1 + 10015c: 7d 83 20 40 cmplw cr3,r3,r4 + 100160: 7d 80 00 26 mfcr r12 + 100164: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpl.map b/src/xenia/cpu/frontend/test/bin/instr_cmpl.map new file mode 100644 index 000000000..817e3550f --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmpl.map @@ -0,0 +1,20 @@ +0000000000000000 t test_cmpld_1 +000000000000000c t test_cmpld_1_constant +0000000000000024 t test_cmpld_2 +0000000000000030 t test_cmpld_2_constant +0000000000000048 t test_cmplw_1 +0000000000000054 t test_cmplw_1_constant +000000000000006c t test_cmplw_2 +0000000000000078 t test_cmplw_2_constant +0000000000000090 t test_cmplw_3 +000000000000009c t test_cmplw_3_constant +00000000000000b0 t test_cmplw_4 +00000000000000bc t test_cmplw_4_constant +00000000000000d0 t test_cmplw_5 +00000000000000dc t test_cmplw_5_constant +00000000000000fc t test_cmplw_6 +0000000000000108 t test_cmplw_6_constant +0000000000000128 t test_cmpl_1 +0000000000000134 t test_cmpl_1_constant +0000000000000148 t test_cmpl_2 +0000000000000154 t test_cmpl_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpli.bin b/src/xenia/cpu/frontend/test/bin/instr_cmpli.bin new file mode 100644 index 0000000000000000000000000000000000000000..b31d1bc4854dd93594a0865fe8db6bba3727f60a GIT binary patch literal 216 zcmdN;W?-sqU{LdGU{J6~U|_6BW: + 100000: 28 23 00 02 cmpldi r3,2 + 100004: 7d 80 00 26 mfcr r12 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 38 60 00 01 li r3,1 + 100010: 78 63 07 c6 rldicr r3,r3,32,31 + 100014: 28 23 00 02 cmpldi r3,2 + 100018: 7d 80 00 26 mfcr r12 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 28 23 00 02 cmpldi r3,2 + 100024: 7d 80 00 26 mfcr r12 + 100028: 4e 80 00 20 blr + +000000000010002c : + 10002c: 38 60 00 01 li r3,1 + 100030: 28 23 00 02 cmpldi r3,2 + 100034: 7d 80 00 26 mfcr r12 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 28 03 00 02 cmplwi r3,2 + 100040: 7d 80 00 26 mfcr r12 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 38 60 00 01 li r3,1 + 10004c: 78 63 07 c6 rldicr r3,r3,32,31 + 100050: 28 03 00 02 cmplwi r3,2 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 28 03 00 01 cmplwi r3,1 + 100060: 7d 80 00 26 mfcr r12 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 60 00 02 li r3,2 + 10006c: 28 03 00 01 cmplwi r3,1 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 28 03 00 01 cmplwi r3,1 + 10007c: 7d 80 00 26 mfcr r12 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 38 60 00 01 li r3,1 + 100088: 78 63 07 c6 rldicr r3,r3,32,31 + 10008c: 78 64 0f a4 rldicr r4,r3,1,62 + 100090: 38 63 00 02 addi r3,r3,2 + 100094: 28 03 00 01 cmplwi r3,1 + 100098: 7d 80 00 26 mfcr r12 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 2a 83 00 02 cmplwi cr5,r3,2 + 1000a4: 7d 80 00 26 mfcr r12 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 60 00 01 li r3,1 + 1000b0: 2a 83 00 02 cmplwi cr5,r3,2 + 1000b4: 7d 80 00 26 mfcr r12 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 29 83 00 01 cmplwi cr3,r3,1 + 1000c0: 7d 80 00 26 mfcr r12 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 60 00 02 li r3,2 + 1000cc: 29 83 00 01 cmplwi cr3,r3,1 + 1000d0: 7d 80 00 26 mfcr r12 + 1000d4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cmpli.map b/src/xenia/cpu/frontend/test/bin/instr_cmpli.map new file mode 100644 index 000000000..bd49541f6 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_cmpli.map @@ -0,0 +1,14 @@ +0000000000000000 t test_cmpldi_1 +000000000000000c t test_cmpldi_1_constant +0000000000000020 t test_cmpldi_2 +000000000000002c t test_cmpldi_2_constant +000000000000003c t test_cmplwi_1 +0000000000000048 t test_cmplwi_1_constant +000000000000005c t test_cmplwi_2 +0000000000000068 t test_cmplwi_2_constant +0000000000000078 t test_cmplwi_5 +0000000000000084 t test_cmplwi_5_constant +00000000000000a0 t test_cmpli_1 +00000000000000ac t test_cmpli_1_constant +00000000000000bc t test_cmpli_2 +00000000000000c8 t test_cmpli_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsb.bin b/src/xenia/cpu/frontend/test/bin/instr_extsb.bin new file mode 100644 index 0000000000000000000000000000000000000000..6d9d762081bd91c0125f85988bc5fe4eb21d9a30 GIT binary patch literal 200 zcmb!gUbT|zehaD literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsb.dis b/src/xenia/cpu/frontend/test/bin/instr_extsb.dis new file mode 100644 index 000000000..3d1cbcca0 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_extsb.dis @@ -0,0 +1,83 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 83 07 74 extsb r3,r4 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 80 00 0f li r4,15 + 10000c: 7c 83 07 74 extsb r3,r4 + 100010: 4e 80 00 20 blr + +0000000000100014 : + 100014: 7c 83 07 74 extsb r3,r4 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 38 80 00 7f li r4,127 + 100020: 7c 83 07 74 extsb r3,r4 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 07 74 extsb r3,r4 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 38 80 00 80 li r4,128 + 100034: 7c 83 07 74 extsb r3,r4 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 7c 83 07 74 extsb r3,r4 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 38 80 0f 7f li r4,3967 + 100048: 7c 84 20 f8 not r4,r4 + 10004c: 7c 83 07 74 extsb r3,r4 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 83 07 75 extsb. r3,r4 + 100058: 7d 80 00 26 mfcr r12 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 38 80 00 0f li r4,15 + 100064: 7c 83 07 75 extsb. r3,r4 + 100068: 7d 80 00 26 mfcr r12 + 10006c: 4e 80 00 20 blr + +0000000000100070 : + 100070: 7c 83 07 75 extsb. r3,r4 + 100074: 7d 80 00 26 mfcr r12 + 100078: 4e 80 00 20 blr + +000000000010007c : + 10007c: 38 80 00 7f li r4,127 + 100080: 7c 83 07 75 extsb. r3,r4 + 100084: 7d 80 00 26 mfcr r12 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 7c 83 07 75 extsb. r3,r4 + 100090: 7d 80 00 26 mfcr r12 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 00 80 li r4,128 + 10009c: 7c 83 07 75 extsb. r3,r4 + 1000a0: 7d 80 00 26 mfcr r12 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 83 07 75 extsb. r3,r4 + 1000ac: 7d 80 00 26 mfcr r12 + 1000b0: 4e 80 00 20 blr + +00000000001000b4 : + 1000b4: 38 80 0f 7f li r4,3967 + 1000b8: 7c 84 20 f8 not r4,r4 + 1000bc: 7c 83 07 75 extsb. r3,r4 + 1000c0: 7d 80 00 26 mfcr r12 + 1000c4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsb.map b/src/xenia/cpu/frontend/test/bin/instr_extsb.map new file mode 100644 index 000000000..9bda0cf75 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_extsb.map @@ -0,0 +1,16 @@ +0000000000000000 t test_extsb_1 +0000000000000008 t test_extsb_1_constant +0000000000000014 t test_extsb_2 +000000000000001c t test_extsb_2_constant +0000000000000028 t test_extsb_3 +0000000000000030 t test_extsb_3_constant +000000000000003c t test_extsb_4 +0000000000000044 t test_extsb_4_constant +0000000000000054 t test_extsb_cr_1 +0000000000000060 t test_extsb_cr_1_constant +0000000000000070 t test_extsb_cr_2 +000000000000007c t test_extsb_cr_2_constant +000000000000008c t test_extsb_cr_3 +0000000000000098 t test_extsb_cr_3_constant +00000000000000a8 t test_extsb_cr_4 +00000000000000b4 t test_extsb_cr_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsh.bin b/src/xenia/cpu/frontend/test/bin/instr_extsh.bin new file mode 100644 index 0000000000000000000000000000000000000000..c93d0377f5d6056d461da40615daabaf39515ba8 GIT binary patch literal 216 zcmbUQ`+6D$S aB=g~XpguSoY7d-`DhIa@hdheCa5VrVjze1j literal 0 HcmV?d00001 diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsh.dis b/src/xenia/cpu/frontend/test/bin/instr_extsh.dis new file mode 100644 index 000000000..4a23be96c --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_extsh.dis @@ -0,0 +1,87 @@ +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 83 07 34 extsh r3,r4 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 80 00 0f li r4,15 + 10000c: 7c 83 07 34 extsh r3,r4 + 100010: 4e 80 00 20 blr + +0000000000100014 : + 100014: 7c 83 07 34 extsh r3,r4 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 38 80 7f ff li r4,32767 + 100020: 7c 83 07 34 extsh r3,r4 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 83 07 34 extsh r3,r4 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 38 80 00 80 li r4,128 + 100034: 78 84 45 e4 rldicr r4,r4,8,55 + 100038: 7c 83 07 34 extsh r3,r4 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 7c 83 07 34 extsh r3,r4 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 38 80 0f 7f li r4,3967 + 10004c: 7c 84 20 f8 not r4,r4 + 100050: 78 84 45 e4 rldicr r4,r4,8,55 + 100054: 7c 83 07 34 extsh r3,r4 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 7c 83 07 35 extsh. r3,r4 + 100060: 7d 80 00 26 mfcr r12 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 00 0f li r4,15 + 10006c: 7c 83 07 35 extsh. r3,r4 + 100070: 7d 80 00 26 mfcr r12 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 83 07 35 extsh. r3,r4 + 10007c: 7d 80 00 26 mfcr r12 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 38 80 7f ff li r4,32767 + 100088: 7c 83 07 35 extsh. r3,r4 + 10008c: 7d 80 00 26 mfcr r12 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 7c 83 07 35 extsh. r3,r4 + 100098: 7d 80 00 26 mfcr r12 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 38 80 00 80 li r4,128 + 1000a4: 78 84 45 e4 rldicr r4,r4,8,55 + 1000a8: 7c 83 07 35 extsh. r3,r4 + 1000ac: 7d 80 00 26 mfcr r12 + 1000b0: 4e 80 00 20 blr + +00000000001000b4 : + 1000b4: 7c 83 07 35 extsh. r3,r4 + 1000b8: 7d 80 00 26 mfcr r12 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 38 80 0f 7f li r4,3967 + 1000c4: 7c 84 20 f8 not r4,r4 + 1000c8: 78 84 45 e4 rldicr r4,r4,8,55 + 1000cc: 7c 83 07 35 extsh. r3,r4 + 1000d0: 7d 80 00 26 mfcr r12 + 1000d4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsh.map b/src/xenia/cpu/frontend/test/bin/instr_extsh.map new file mode 100644 index 000000000..9a5355255 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_extsh.map @@ -0,0 +1,16 @@ +0000000000000000 t test_extsh_1 +0000000000000008 t test_extsh_1_constant +0000000000000014 t test_extsh_2 +000000000000001c t test_extsh_2_constant +0000000000000028 t test_extsh_3 +0000000000000030 t test_extsh_3_constant +0000000000000040 t test_extsh_4 +0000000000000048 t test_extsh_4_constant +000000000000005c t test_extsh_cr_1 +0000000000000068 t test_extsh_cr_1_constant +0000000000000078 t test_extsh_cr_2 +0000000000000084 t test_extsh_cr_2_constant +0000000000000094 t test_extsh_cr_3 +00000000000000a0 t test_extsh_cr_3_constant +00000000000000b4 t test_extsh_cr_4 +00000000000000c0 t test_extsh_cr_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsw.bin b/src/xenia/cpu/frontend/test/bin/instr_extsw.bin new file mode 100644 index 0000000000000000000000000000000000000000..31e528a1299872f062cc17525f3a2c54acb7ca63 GIT binary patch literal 224 zcmb: + 100000: 7c 83 07 b4 extsw r3,r4 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 38 80 00 0f li r4,15 + 10000c: 7c 83 07 b4 extsw r3,r4 + 100010: 4e 80 00 20 blr + +0000000000100014 : + 100014: 7c 83 07 b4 extsw r3,r4 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 3c 80 7f ff lis r4,32767 + 100020: 60 84 ff ff ori r4,r4,65535 + 100024: 7c 83 07 b4 extsw r3,r4 + 100028: 4e 80 00 20 blr + +000000000010002c : + 10002c: 7c 83 07 b4 extsw r3,r4 + 100030: 4e 80 00 20 blr + +0000000000100034 : + 100034: 38 80 00 80 li r4,128 + 100038: 78 84 c1 e4 rldicr r4,r4,24,39 + 10003c: 7c 83 07 b4 extsw r3,r4 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 7c 83 07 b4 extsw r3,r4 + 100048: 4e 80 00 20 blr + +000000000010004c : + 10004c: 38 80 0f 7f li r4,3967 + 100050: 7c 84 20 f8 not r4,r4 + 100054: 78 84 c1 e4 rldicr r4,r4,24,39 + 100058: 7c 83 07 b4 extsw r3,r4 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 07 b5 extsw. r3,r4 + 100064: 7d 80 00 26 mfcr r12 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 00 0f li r4,15 + 100070: 7c 83 07 b5 extsw. r3,r4 + 100074: 7d 80 00 26 mfcr r12 + 100078: 4e 80 00 20 blr + +000000000010007c : + 10007c: 7c 83 07 b5 extsw. r3,r4 + 100080: 7d 80 00 26 mfcr r12 + 100084: 4e 80 00 20 blr + +0000000000100088 : + 100088: 3c 80 7f ff lis r4,32767 + 10008c: 60 84 ff ff ori r4,r4,65535 + 100090: 7c 83 07 b5 extsw. r3,r4 + 100094: 7d 80 00 26 mfcr r12 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 7c 83 07 b5 extsw. r3,r4 + 1000a0: 7d 80 00 26 mfcr r12 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 38 80 00 80 li r4,128 + 1000ac: 78 84 c1 e4 rldicr r4,r4,24,39 + 1000b0: 7c 83 07 b5 extsw. r3,r4 + 1000b4: 7d 80 00 26 mfcr r12 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 7c 83 07 b5 extsw. r3,r4 + 1000c0: 7d 80 00 26 mfcr r12 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 80 0f 7f li r4,3967 + 1000cc: 7c 84 20 f8 not r4,r4 + 1000d0: 78 84 c1 e4 rldicr r4,r4,24,39 + 1000d4: 7c 83 07 b5 extsw. r3,r4 + 1000d8: 7d 80 00 26 mfcr r12 + 1000dc: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_extsw.map b/src/xenia/cpu/frontend/test/bin/instr_extsw.map new file mode 100644 index 000000000..c32758638 --- /dev/null +++ b/src/xenia/cpu/frontend/test/bin/instr_extsw.map @@ -0,0 +1,16 @@ +0000000000000000 t test_extsw_1 +0000000000000008 t test_extsw_1_constant +0000000000000014 t test_extsw_2 +000000000000001c t test_extsw_2_constant +000000000000002c t test_extsw_3 +0000000000000034 t test_extsw_3_constant +0000000000000044 t test_extsw_4 +000000000000004c t test_extsw_4_constant +0000000000000060 t test_extsw_cr_1 +000000000000006c t test_extsw_cr_1_constant +000000000000007c t test_extsw_cr_2 +0000000000000088 t test_extsw_cr_2_constant +000000000000009c t test_extsw_cr_3 +00000000000000a8 t test_extsw_cr_3_constant +00000000000000bc t test_extsw_cr_4 +00000000000000c8 t test_extsw_cr_4_constant diff --git a/src/xenia/cpu/frontend/test/instr_andi.s b/src/xenia/cpu/frontend/test/instr_andi.s index c36690a02..8644bc074 100644 --- a/src/xenia/cpu/frontend/test/instr_andi.s +++ b/src/xenia/cpu/frontend/test/instr_andi.s @@ -16,23 +16,23 @@ test_andi_cr_1_constant: #_ REGISTER_OUT r11 0x0000CAFE #_ REGISTER_OUT r12 0x40000000 -#test_andi_cr_2: -# #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF -# andi. r11, r5, 0 -# mfcr r12 -# blr -# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF -# #_ REGISTER_OUT r11 0 -# #_ REGISTER_OUT r12 0x20000000 +test_andi_cr_2: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + andi. r11, r5, 0 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 -#test_andi_cr_2_constant: -# #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF -# andi. r11, r5, 0 -# mfcr r12 -# blr -# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF -# #_ REGISTER_OUT r11 0 -# #_ REGISTER_OUT r12 0x20000000 +test_andi_cr_2_constant: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + andi. r11, r5, 0 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 test_andi_cr_3: #_ REGISTER_IN r5 0 diff --git a/src/xenia/cpu/frontend/test/instr_andis.s b/src/xenia/cpu/frontend/test/instr_andis.s index 3ae50397b..425f72de0 100644 --- a/src/xenia/cpu/frontend/test/instr_andis.s +++ b/src/xenia/cpu/frontend/test/instr_andis.s @@ -16,23 +16,23 @@ test_andis_cr_1_constant: #_ REGISTER_OUT r11 0xCAFE0000 #_ REGISTER_OUT r12 0x80000000 -#test_andis_cr_2: -# #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF -# andis. r11, r5, 0 -# mfcr r12 -# blr -# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF -# #_ REGISTER_OUT r11 0 -# #_ REGISTER_OUT r12 0x20000000 +test_andis_cr_2: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + andis. r11, r5, 0 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 -#test_andis_cr_2_constant: -# #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF -# andis. r11, r5, 0 -# mfcr r12 -# blr -# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF -# #_ REGISTER_OUT r11 0 -# #_ REGISTER_OUT r12 0x20000000 +test_andis_cr_2_constant: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + andis. r11, r5, 0 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 test_andis_cr_3: #_ REGISTER_IN r5 0 diff --git a/src/xenia/cpu/hir/hir_builder.cc b/src/xenia/cpu/hir/hir_builder.cc index a52392914..f98d81331 100644 --- a/src/xenia/cpu/hir/hir_builder.cc +++ b/src/xenia/cpu/hir/hir_builder.cc @@ -1196,7 +1196,8 @@ Value* HIRBuilder::CompareXX(const OpcodeInfo& opcode, Value* value1, Value* value2) { ASSERT_TYPES_EQUAL(value1, value2); if (value1->IsConstant() && value2->IsConstant()) { - return LoadConstant(value1->Compare(opcode.num, value2) ? 1 : 0); + return LoadConstant(value1->Compare(opcode.num, value2) ? int8_t(1) + : int8_t(0)); } Instr* i = AppendInstr(opcode, 0, AllocValue(INT8_TYPE)); diff --git a/src/xenia/cpu/hir/value.cc b/src/xenia/cpu/hir/value.cc index f674cabee..bedef09c2 100644 --- a/src/xenia/cpu/hir/value.cc +++ b/src/xenia/cpu/hir/value.cc @@ -244,7 +244,7 @@ bool Value::Add(Value* other) { } bool Value::Sub(Value* other) { -#define SUB_DID_CARRY(a, b) (b == 0 || a > (~(0-b))) +#define SUB_DID_CARRY(a, b) (b == 0 || a > (~(0 - b))) assert_true(type == other->type); bool did_carry = false; switch (type) { @@ -313,9 +313,12 @@ void Value::MulHi(Value* other, bool is_unsigned) { switch (type) { case INT32_TYPE: if (is_unsigned) { - constant.i32 = (int32_t)(((uint64_t)((uint32_t)constant.i32) * (uint32_t)other->constant.i32) >> 32); + constant.i32 = (int32_t)(((uint64_t)((uint32_t)constant.i32) * + (uint32_t)other->constant.i32) >> + 32); } else { - constant.i32 = (int32_t)(((int64_t)constant.i32 * (int64_t)other->constant.i32) >> 32); + constant.i32 = (int32_t)( + ((int64_t)constant.i32 * (int64_t)other->constant.i32) >> 32); } break; case INT64_TYPE: @@ -670,9 +673,132 @@ void Value::CountLeadingZeros(const Value* other) { } bool Value::Compare(Opcode opcode, Value* other) { - // TODO(benvanik): big matrix. - assert_always(); - return false; + assert_true(type == other->type); + switch (other->type) { + case INT8_TYPE: + return CompareInt8(opcode, this, other); + case INT16_TYPE: + return CompareInt16(opcode, this, other); + case INT32_TYPE: + return CompareInt32(opcode, this, other); + case INT64_TYPE: + return CompareInt64(opcode, this, other); + default: + assert_unhandled_case(type); + return false; + } +} + +bool Value::CompareInt8(Opcode opcode, Value* a, Value* b) { + switch (opcode) { + case OPCODE_COMPARE_EQ: + return a->constant.i8 == b->constant.i8; + case OPCODE_COMPARE_NE: + return a->constant.i8 != b->constant.i8; + case OPCODE_COMPARE_SLT: + return a->constant.i8 < b->constant.i8; + case OPCODE_COMPARE_SLE: + return a->constant.i8 <= b->constant.i8; + case OPCODE_COMPARE_SGT: + return a->constant.i8 > b->constant.i8; + case OPCODE_COMPARE_SGE: + return a->constant.i8 >= b->constant.i8; + case OPCODE_COMPARE_ULT: + return uint8_t(a->constant.i8) < uint8_t(b->constant.i8); + case OPCODE_COMPARE_ULE: + return uint8_t(a->constant.i8) <= uint8_t(b->constant.i8); + case OPCODE_COMPARE_UGT: + return uint8_t(a->constant.i8) > uint8_t(b->constant.i8); + case OPCODE_COMPARE_UGE: + return uint8_t(a->constant.i8) >= uint8_t(b->constant.i8); + default: + assert_unhandled_case(opcode); + return false; + } +} + +bool Value::CompareInt16(Opcode opcode, Value* a, Value* b) { + switch (opcode) { + case OPCODE_COMPARE_EQ: + return a->constant.i16 == b->constant.i16; + case OPCODE_COMPARE_NE: + return a->constant.i16 != b->constant.i16; + case OPCODE_COMPARE_SLT: + return a->constant.i16 < b->constant.i16; + case OPCODE_COMPARE_SLE: + return a->constant.i16 <= b->constant.i16; + case OPCODE_COMPARE_SGT: + return a->constant.i16 > b->constant.i16; + case OPCODE_COMPARE_SGE: + return a->constant.i16 >= b->constant.i16; + case OPCODE_COMPARE_ULT: + return uint16_t(a->constant.i16) < uint16_t(b->constant.i16); + case OPCODE_COMPARE_ULE: + return uint16_t(a->constant.i16) <= uint16_t(b->constant.i16); + case OPCODE_COMPARE_UGT: + return uint16_t(a->constant.i16) > uint16_t(b->constant.i16); + case OPCODE_COMPARE_UGE: + return uint16_t(a->constant.i16) >= uint16_t(b->constant.i16); + default: + assert_unhandled_case(opcode); + return false; + } +} + +bool Value::CompareInt32(Opcode opcode, Value* a, Value* b) { + switch (opcode) { + case OPCODE_COMPARE_EQ: + return a->constant.i32 == b->constant.i32; + case OPCODE_COMPARE_NE: + return a->constant.i32 != b->constant.i32; + case OPCODE_COMPARE_SLT: + return a->constant.i32 < b->constant.i32; + case OPCODE_COMPARE_SLE: + return a->constant.i32 <= b->constant.i32; + case OPCODE_COMPARE_SGT: + return a->constant.i32 > b->constant.i32; + case OPCODE_COMPARE_SGE: + return a->constant.i32 >= b->constant.i32; + case OPCODE_COMPARE_ULT: + return uint32_t(a->constant.i32) < uint32_t(b->constant.i32); + case OPCODE_COMPARE_ULE: + return uint32_t(a->constant.i32) <= uint32_t(b->constant.i32); + case OPCODE_COMPARE_UGT: + return uint32_t(a->constant.i32) > uint32_t(b->constant.i32); + case OPCODE_COMPARE_UGE: + return uint32_t(a->constant.i32) >= uint32_t(b->constant.i32); + default: + assert_unhandled_case(opcode); + return false; + } +} + +bool Value::CompareInt64(Opcode opcode, Value* a, Value* b) { + switch (opcode) { + case OPCODE_COMPARE_EQ: + return a->constant.i64 == b->constant.i64; + case OPCODE_COMPARE_NE: + return a->constant.i64 != b->constant.i64; + case OPCODE_COMPARE_SLT: + return a->constant.i64 < b->constant.i64; + case OPCODE_COMPARE_SLE: + return a->constant.i64 <= b->constant.i64; + case OPCODE_COMPARE_SGT: + return a->constant.i64 > b->constant.i64; + case OPCODE_COMPARE_SGE: + return a->constant.i64 >= b->constant.i64; + case OPCODE_COMPARE_ULT: + return uint64_t(a->constant.i64) < uint64_t(b->constant.i64); + case OPCODE_COMPARE_ULE: + return uint64_t(a->constant.i64) <= uint64_t(b->constant.i64); + case OPCODE_COMPARE_UGT: + return uint64_t(a->constant.i64) > uint64_t(b->constant.i64); + case OPCODE_COMPARE_UGE: + return uint64_t(a->constant.i64) >= uint64_t(b->constant.i64); + default: + assert_unhandled_case(opcode); + return false; + } } } // namespace hir diff --git a/src/xenia/cpu/hir/value.h b/src/xenia/cpu/hir/value.h index ea0db6d01..0d76d6a13 100644 --- a/src/xenia/cpu/hir/value.h +++ b/src/xenia/cpu/hir/value.h @@ -403,6 +403,12 @@ class Value { void ByteSwap(); void CountLeadingZeros(const Value* other); bool Compare(Opcode opcode, Value* other); + + private: + static bool CompareInt8(Opcode opcode, Value* a, Value* b); + static bool CompareInt16(Opcode opcode, Value* a, Value* b); + static bool CompareInt32(Opcode opcode, Value* a, Value* b); + static bool CompareInt64(Opcode opcode, Value* a, Value* b); }; } // namespace hir