From de040f0b42828ad00eadd90e19caf96e7fb3b1b8 Mon Sep 17 00:00:00 2001 From: Wunkolo Date: Fri, 10 May 2024 20:49:42 -0700 Subject: [PATCH] [a64] Fix `OPCODE_SPLAT` Writing to the wrong register! --- src/xenia/cpu/backend/a64/a64_seq_vector.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/xenia/cpu/backend/a64/a64_seq_vector.cc b/src/xenia/cpu/backend/a64/a64_seq_vector.cc index 030d846e1..4e90efe7d 100644 --- a/src/xenia/cpu/backend/a64/a64_seq_vector.cc +++ b/src/xenia/cpu/backend/a64/a64_seq_vector.cc @@ -1062,9 +1062,9 @@ struct SPLAT_I8 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { e.MOV(W0, i.src1.constant()); - e.DUP(Q0.B16(), W0); + e.DUP(i.dest.reg().B16(), W0); } else { - e.DUP(Q0.B16(), i.src1); + e.DUP(i.dest.reg().B16(), i.src1); } } }; @@ -1072,9 +1072,9 @@ struct SPLAT_I16 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { e.MOV(W0, i.src1.constant()); - e.DUP(Q0.H8(), W0); + e.DUP(i.dest.reg().H8(), W0); } else { - e.DUP(Q0.H8(), i.src1); + e.DUP(i.dest.reg().H8(), i.src1); } } }; @@ -1082,9 +1082,9 @@ struct SPLAT_I32 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { e.MOV(W0, i.src1.constant()); - e.DUP(Q0.S4(), W0); + e.DUP(i.dest.reg().S4(), W0); } else { - e.DUP(Q0.S4(), i.src1); + e.DUP(i.dest.reg().S4(), i.src1); } } }; @@ -1092,9 +1092,9 @@ struct SPLAT_F32 : Sequence> { static void Emit(A64Emitter& e, const EmitArgType& i) { if (i.src1.is_constant) { e.MOV(W0, i.src1.value->constant.i32); - e.DUP(Q0.S4(), W0); + e.DUP(i.dest.reg().S4(), W0); } else { - e.DUP(Q0.S4(), i.src1.reg().toQ().Selem()[0]); + e.DUP(i.dest.reg().S4(), i.src1.reg().toQ().Selem()[0]); } } };