diff --git a/src/xenia/cpu/backend/x64/x64_backend.cc b/src/xenia/cpu/backend/x64/x64_backend.cc
index beed2af8e..4e6356959 100644
--- a/src/xenia/cpu/backend/x64/x64_backend.cc
+++ b/src/xenia/cpu/backend/x64/x64_backend.cc
@@ -82,8 +82,6 @@ bool X64Backend::Initialize(Processor* processor) {
     return false;
   }
 
-  RegisterSequences();
-
   // Need movbe to do advanced LOAD/STORE tricks.
   if (FLAGS_enable_haswell_instructions) {
     machine_info_.supports_extended_load_store =
diff --git a/src/xenia/cpu/backend/x64/x64_seq_control.cc b/src/xenia/cpu/backend/x64/x64_seq_control.cc
index 81d2d9ab6..80eeeebc7 100644
--- a/src/xenia/cpu/backend/x64/x64_seq_control.cc
+++ b/src/xenia/cpu/backend/x64/x64_seq_control.cc
@@ -19,7 +19,7 @@ namespace cpu {
 namespace backend {
 namespace x64 {
 
-void RegisterControl() {}
+volatile int anchor_control = 0;
 
 // ============================================================================
 // OPCODE_DEBUG_BREAK
diff --git a/src/xenia/cpu/backend/x64/x64_seq_memory.cc b/src/xenia/cpu/backend/x64/x64_seq_memory.cc
index aec6218fc..7526d1fc8 100644
--- a/src/xenia/cpu/backend/x64/x64_seq_memory.cc
+++ b/src/xenia/cpu/backend/x64/x64_seq_memory.cc
@@ -20,7 +20,7 @@ namespace cpu {
 namespace backend {
 namespace x64 {
 
-void RegisterMemory() {}
+volatile int anchor_memory = 0;
 
 // Note: all types are always aligned in the context.
 RegExp ComputeContextAddress(X64Emitter& e, const OffsetOp& offset) {
diff --git a/src/xenia/cpu/backend/x64/x64_seq_vector.cc b/src/xenia/cpu/backend/x64/x64_seq_vector.cc
index bfd3e76fe..89d3bee14 100644
--- a/src/xenia/cpu/backend/x64/x64_seq_vector.cc
+++ b/src/xenia/cpu/backend/x64/x64_seq_vector.cc
@@ -22,7 +22,7 @@ namespace cpu {
 namespace backend {
 namespace x64 {
 
-void RegisterVector() {}
+volatile int anchor_vector = 0;
 
 // ============================================================================
 // OPCODE_VECTOR_CONVERT_I2F
diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc
index 0fff6d458..7d18cb4d0 100644
--- a/src/xenia/cpu/backend/x64/x64_sequences.cc
+++ b/src/xenia/cpu/backend/x64/x64_sequences.cc
@@ -3057,11 +3057,15 @@ struct SET_ROUNDING_MODE_I32
 };
 EMITTER_OPCODE_TABLE(OPCODE_SET_ROUNDING_MODE, SET_ROUNDING_MODE_I32);
 
-void RegisterSequences() {
-  RegisterControl();
-  RegisterMemory();
-  RegisterVector();
-}
+// Include anchors to other sequence sources so they get included in the build.
+extern volatile int anchor_control;
+static int anchor_control_dest = anchor_control;
+
+extern volatile int anchor_memory;
+static int anchor_memory_dest = anchor_memory;
+
+extern volatile int anchor_vector;
+static int anchor_vector_dest = anchor_vector;
 
 bool SelectSequence(X64Emitter* e, const Instr* i, const Instr** new_tail) {
   const InstrKey key(i);
diff --git a/src/xenia/cpu/backend/x64/x64_sequences.h b/src/xenia/cpu/backend/x64/x64_sequences.h
index 5815a3a92..07b264ab2 100644
--- a/src/xenia/cpu/backend/x64/x64_sequences.h
+++ b/src/xenia/cpu/backend/x64/x64_sequences.h
@@ -40,12 +40,6 @@ static bool Register() {
 #define EMITTER_OPCODE_TABLE(name, ...) \
   const auto X64_INSTR_##name = Register<__VA_ARGS__>();
 
-// Registration functions to force inclusion of several files
-void RegisterControl();
-void RegisterMemory();
-void RegisterVector();
-
-void RegisterSequences();
 bool SelectSequence(X64Emitter* e, const hir::Instr* i,
                     const hir::Instr** new_tail);