From dc1b1ca638c4c83f5b2c76275a98ded365ec810b Mon Sep 17 00:00:00 2001 From: gibbed Date: Wed, 13 May 2015 00:21:43 -0500 Subject: [PATCH] Constant tests for add, addc, adde. --- src/xenia/cpu/frontend/test/instr_add.s | 24 +++++ src/xenia/cpu/frontend/test/instr_addc.s | 57 +++++++++++ src/xenia/cpu/frontend/test/instr_adde.s | 125 +++++++++++++++++++++++ 3 files changed, 206 insertions(+) diff --git a/src/xenia/cpu/frontend/test/instr_add.s b/src/xenia/cpu/frontend/test/instr_add.s index 805086bf6..0f830f978 100644 --- a/src/xenia/cpu/frontend/test/instr_add.s +++ b/src/xenia/cpu/frontend/test/instr_add.s @@ -9,6 +9,18 @@ test_add_1: #_ REGISTER_OUT r25 0x0000FFFF #_ REGISTER_OUT r11 0x0010FFFF +test_add_1_constant: + lis r5, 0x10 + li r25, -1 + clrldi r25, r25, 48 + + add r11, r5, r25 + + blr + #_ REGISTER_OUT r5 0x00100000 + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0010FFFF + test_add_2: #_ REGISTER_IN r0 0x00100000 #_ REGISTER_IN r25 0x0000FFFF @@ -19,3 +31,15 @@ test_add_2: #_ REGISTER_OUT r0 0x00100000 #_ REGISTER_OUT r25 0x0000FFFF #_ REGISTER_OUT r11 0x0010FFFF + +test_add_2_constant: + lis r0, 0x10 + li r25, -1 + clrldi r25, r25, 48 + + add r11, r0, r25 + + blr + #_ REGISTER_OUT r0 0x00100000 + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0010FFFF diff --git a/src/xenia/cpu/frontend/test/instr_addc.s b/src/xenia/cpu/frontend/test/instr_addc.s index 75fa41c7a..6d03d9550 100644 --- a/src/xenia/cpu/frontend/test/instr_addc.s +++ b/src/xenia/cpu/frontend/test/instr_addc.s @@ -1,3 +1,5 @@ +# constant tests are commented since add_carry isn't supported + test_addc_1: #_ REGISTER_IN r4 1 #_ REGISTER_IN r5 2 @@ -9,6 +11,17 @@ test_addc_1: #_ REGISTER_OUT r5 2 #_ REGISTER_OUT r6 0 +#test_addc_1_constant: +# li r4, 1 +# li r5, 2 +# addc r3, r4, r5 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r3 3 +# #_ REGISTER_OUT r4 1 +# #_ REGISTER_OUT r5 2 +# #_ REGISTER_OUT r6 0 + test_addc_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -20,6 +33,17 @@ test_addc_2: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +#test_addc_2_constant: +# li r4, -1 +# li r5, 0 +# addc r3, r4, r5 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF +# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF +# #_ REGISTER_OUT r5 0 +# #_ REGISTER_OUT r6 0 + test_addc_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -31,6 +55,17 @@ test_addc_3: #_ REGISTER_OUT r5 1 #_ REGISTER_OUT r6 1 +#test_addc_3_constant: +# li r4, -1 +# li r5, 1 +# addc r3, r4, r5 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r3 0 +# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF +# #_ REGISTER_OUT r5 1 +# #_ REGISTER_OUT r6 1 + test_addc_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 123 @@ -42,6 +77,17 @@ test_addc_4: #_ REGISTER_OUT r5 123 #_ REGISTER_OUT r6 1 +#test_addc_4_constant: +# li r4, -1 +# li r5, 123 +# addc r3, r4, r5 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r3 0x000000000000007A +# #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF +# #_ REGISTER_OUT r5 123 +# #_ REGISTER_OUT r6 1 + test_addc_5: #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -52,3 +98,14 @@ test_addc_5: #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 + +#test_addc_5_constant: +# li r4, -1 +# sldi r5, r4, 1 +# addc r3, r4, r5 +# adde r6, r0, r0 +# blr +# #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE +# #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF +# #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF +# #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_adde.s b/src/xenia/cpu/frontend/test/instr_adde.s index d6c93a1f5..e302a3c3f 100644 --- a/src/xenia/cpu/frontend/test/instr_adde.s +++ b/src/xenia/cpu/frontend/test/instr_adde.s @@ -9,6 +9,17 @@ test_adde_1: #_ REGISTER_OUT r5 2 #_ REGISTER_OUT r6 0 +test_adde_1_constant: + li r4, 1 + li r5, 2 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 3 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + #_ REGISTER_OUT r6 0 + test_adde_2: #_ REGISTER_IN r4 1 #_ REGISTER_IN r5 2 @@ -23,6 +34,20 @@ test_adde_2: #_ REGISTER_OUT r5 2 #_ REGISTER_OUT r6 0 +test_adde_2_constant: + li r4, 1 + li r5, 2 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 4 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + #_ REGISTER_OUT r6 0 + test_adde_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -34,6 +59,17 @@ test_adde_3: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +test_adde_3_constant: + li r4, -1 + li r5, 0 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + test_adde_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -48,6 +84,20 @@ test_adde_4: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 1 +test_adde_4_constant: + li r4, -1 + li r5, 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 1 + test_adde_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -59,6 +109,17 @@ test_adde_5: #_ REGISTER_OUT r5 1 #_ REGISTER_OUT r6 1 +test_adde_5_constant: + li r4, -1 + li r5, 1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + test_adde_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -73,6 +134,20 @@ test_adde_6: #_ REGISTER_OUT r5 1 #_ REGISTER_OUT r6 1 +test_adde_6_constant: + li r4, -1 + li r5, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + test_adde_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 123 @@ -84,6 +159,17 @@ test_adde_7: #_ REGISTER_OUT r5 123 #_ REGISTER_OUT r6 1 +test_adde_7_constant: + li r4, -1 + li r5, 123 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x000000000000007A + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 123 + #_ REGISTER_OUT r6 1 + test_adde_8: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 123 @@ -98,6 +184,20 @@ test_adde_8: #_ REGISTER_OUT r5 123 #_ REGISTER_OUT r6 1 +test_adde_8_constant: + li r4, -1 + li r5, 123 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x000000000000007B + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 123 + #_ REGISTER_OUT r6 1 + test_adde_9: #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -109,6 +209,17 @@ test_adde_9: #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_adde_9_constant: + li r5, -1 + sldi r4, r5, 1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_adde_10: #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF @@ -122,3 +233,17 @@ test_adde_10: #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 + +test_adde_10_constant: + li r5, -1 + sldi r4, r5, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1