fctiw[z]x: Sign-extend the result (verified by HW)
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8ccefa1600
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cff80bd782
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@ -261,7 +261,7 @@ int InstrEmit_fctiwx(PPCHIRBuilder& f, const InstrData& i) {
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// TODO(benvanik): pull from FPSCR[RN]
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// TODO(benvanik): pull from FPSCR[RN]
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RoundMode round_mode = ROUND_TO_ZERO;
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RoundMode round_mode = ROUND_TO_ZERO;
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Value* v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
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Value* v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
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v = f.Cast(f.ZeroExtend(v, INT64_TYPE), FLOAT64_TYPE);
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v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
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f.StoreFPR(i.X.RT, v);
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f.StoreFPR(i.X.RT, v);
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f.UpdateFPSCR(v, i.X.Rc);
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f.UpdateFPSCR(v, i.X.Rc);
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return 0;
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return 0;
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@ -45,7 +45,7 @@ test_fctiwz_6:
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fctiwz f1, f0
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fctiwz f1, f0
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blr
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blr
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#_ REGISTER_OUT f0 0xbff0000000000000
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#_ REGISTER_OUT f0 0xbff0000000000000
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#_ REGISTER_OUT f1 0x00000000ffffffff
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#_ REGISTER_OUT f1 0xffffffffffffffff
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# -(2^31)
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# -(2^31)
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test_fctiwz_7:
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test_fctiwz_7:
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@ -53,7 +53,7 @@ test_fctiwz_7:
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fctiwz f1, f0
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fctiwz f1, f0
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blr
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blr
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#_ REGISTER_OUT f0 0xc1e0000000000000
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#_ REGISTER_OUT f0 0xc1e0000000000000
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#_ REGISTER_OUT f1 0x0000000080000000
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#_ REGISTER_OUT f1 0xFFFFFFFF80000000
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# 2^31 - 1
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# 2^31 - 1
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test_fctiwz_8:
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test_fctiwz_8:
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@ -77,7 +77,7 @@ test_fctiwz_10:
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fctiwz f1, f0
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fctiwz f1, f0
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blr
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blr
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#_ REGISTER_OUT f0 0xfff0000000000000
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#_ REGISTER_OUT f0 0xfff0000000000000
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#_ REGISTER_OUT f1 0x0000000080000000
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#_ REGISTER_OUT f1 0xFFFFFFFF80000000
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# TODO(DrChat): Xenia doesn't handle NaNs yet.
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# TODO(DrChat): Xenia doesn't handle NaNs yet.
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# # QNaN
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# # QNaN
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@ -86,7 +86,7 @@ test_fctiwz_10:
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# fctiwz f1, f0
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# fctiwz f1, f0
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# blr
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# blr
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# #_ REGISTER_OUT f0 0xfff8000000000000
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# #_ REGISTER_OUT f0 0xfff8000000000000
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# #_ REGISTER_OUT f1 0x0000000080000000
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# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
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#
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#
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# # SNaN
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# # SNaN
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# test_fctiwz_12:
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# test_fctiwz_12:
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@ -94,7 +94,7 @@ test_fctiwz_10:
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# fctiwz f1, f0
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# fctiwz f1, f0
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# blr
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# blr
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# #_ REGISTER_OUT f0 0xfff4000000000000
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# #_ REGISTER_OUT f0 0xfff4000000000000
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# #_ REGISTER_OUT f1 0x0000000080000000
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# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
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# +0
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# +0
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test_fctidz_1:
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test_fctidz_1:
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