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fctiw[z]x: Sign-extend the result (verified by HW)

This commit is contained in:
DrChat 2017-04-26 12:28:35 -05:00
parent 8ccefa1600
commit cff80bd782
2 changed files with 6 additions and 6 deletions
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2
src/xenia/cpu/ppc/ppc_emit_fpu.cc
View File

@ -261,7 +261,7 @@ int InstrEmit_fctiwx(PPCHIRBuilder& f, const InstrData& i) {
// TODO(benvanik): pull from FPSCR[RN]
RoundMode round_mode = ROUND_TO_ZERO;
Value* v = f.Convert(f.LoadFPR(i.X.RB), INT32_TYPE, round_mode);
v = f.Cast(f.ZeroExtend(v, INT64_TYPE), FLOAT64_TYPE);
v = f.Cast(f.SignExtend(v, INT64_TYPE), FLOAT64_TYPE);
f.StoreFPR(i.X.RT, v);
f.UpdateFPSCR(v, i.X.Rc);
return 0;

10
src/xenia/cpu/ppc/testing/instr_fctixz.s
View File

@ -45,7 +45,7 @@ test_fctiwz_6:
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xbff0000000000000
#_ REGISTER_OUT f1 0x00000000ffffffff
#_ REGISTER_OUT f1 0xffffffffffffffff
# -(2^31)
test_fctiwz_7:
@ -53,7 +53,7 @@ test_fctiwz_7:
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xc1e0000000000000
#_ REGISTER_OUT f1 0x0000000080000000
#_ REGISTER_OUT f1 0xFFFFFFFF80000000
# 2^31 - 1
test_fctiwz_8:
@ -77,7 +77,7 @@ test_fctiwz_10:
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xfff0000000000000
#_ REGISTER_OUT f1 0x0000000080000000
#_ REGISTER_OUT f1 0xFFFFFFFF80000000
# TODO(DrChat): Xenia doesn't handle NaNs yet.
# # QNaN
@ -86,7 +86,7 @@ test_fctiwz_10:
# fctiwz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff8000000000000
# #_ REGISTER_OUT f1 0x0000000080000000
# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
#
# # SNaN
# test_fctiwz_12:
@ -94,7 +94,7 @@ test_fctiwz_10:
# fctiwz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff4000000000000
# #_ REGISTER_OUT f1 0x0000000080000000
# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
# +0
test_fctidz_1: