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fsel test.

This commit is contained in:
Ben Vanik 2015-01-11 21:01:25 -08:00
parent 6a44cf9662
commit cd4e877ae1
5 changed files with 53 additions and 2 deletions
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3
src/alloy/frontend/ppc/ppc_emit_alu.cc
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@ -732,8 +732,7 @@ XEEMITTER(extswx, 0x7C0007B4, X)(PPCHIRBuilder& f, InstrData& i) {
XEEMITTER(nandx, 0x7C0003B8, X)(PPCHIRBuilder& f, InstrData& i) {
// RA <- ¬((RS) & (RB))
Value* ra = f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
ra = f.Not(ra);
Value* ra = f.Not(f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)));
f.StoreGPR(i.X.RA, ra);
if (i.X.Rc) {
f.UpdateCR(0, ra);

BIN
src/alloy/frontend/ppc/test/bin/instr_fsel.bin Normal file
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17
src/alloy/frontend/ppc/test/bin/instr_fsel.dis Normal file
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@ -0,0 +1,17 @@
/vagrant/src/alloy/frontend/ppc/test/bin//instr_fsel.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_fsel_1>:
100000: fc 22 20 ee fsel f1,f2,f3,f4
100004: 4e 80 00 20 blr
0000000000100008 <test_fsel_2>:
100008: fc 22 20 ee fsel f1,f2,f3,f4
10000c: 4e 80 00 20 blr
0000000000100010 <test_fsel_3>:
100010: fc 22 20 ee fsel f1,f2,f3,f4
100014: 4e 80 00 20 blr

3
src/alloy/frontend/ppc/test/bin/instr_fsel.map Normal file
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@ -0,0 +1,3 @@
0000000000000000 t test_fsel_1
0000000000000008 t test_fsel_2
0000000000000010 t test_fsel_3

32
src/alloy/frontend/ppc/test/instr_fsel.s Normal file
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@ -0,0 +1,32 @@
test_fsel_1:
#_ REGISTER_IN f2 2.0
#_ REGISTER_IN f3 3.0
#_ REGISTER_IN f4 4.0
fsel f1, f2, f3, f4
blr
#_ REGISTER_OUT f1 3.0
#_ REGISTER_OUT f2 2.0
#_ REGISTER_OUT f3 3.0
#_ REGISTER_OUT f4 4.0
test_fsel_2:
#_ REGISTER_IN f2 -2.0
#_ REGISTER_IN f3 3.0
#_ REGISTER_IN f4 4.0
fsel f1, f2, f3, f4
blr
#_ REGISTER_OUT f1 4.0
#_ REGISTER_OUT f2 -2.0
#_ REGISTER_OUT f3 3.0
#_ REGISTER_OUT f4 4.0
test_fsel_3:
#_ REGISTER_IN f2 0.0
#_ REGISTER_IN f3 3.0
#_ REGISTER_IN f4 4.0
fsel f1, f2, f3, f4
blr
#_ REGISTER_OUT f1 3.0
#_ REGISTER_OUT f2 0.0
#_ REGISTER_OUT f3 3.0
#_ REGISTER_OUT f4 4.0