From cd4e877ae1c37f419bf8d0c53399896bf8061a56 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sun, 11 Jan 2015 21:01:25 -0800 Subject: [PATCH] fsel test. --- src/alloy/frontend/ppc/ppc_emit_alu.cc | 3 +- .../frontend/ppc/test/bin/instr_fsel.bin | Bin 0 -> 24 bytes .../frontend/ppc/test/bin/instr_fsel.dis | 17 ++++++++++ .../frontend/ppc/test/bin/instr_fsel.map | 3 ++ src/alloy/frontend/ppc/test/instr_fsel.s | 32 ++++++++++++++++++ 5 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 src/alloy/frontend/ppc/test/bin/instr_fsel.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_fsel.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_fsel.map create mode 100644 src/alloy/frontend/ppc/test/instr_fsel.s diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc index 94af993ba..bf1b5ed44 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc @@ -732,8 +732,7 @@ XEEMITTER(extswx, 0x7C0007B4, X)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(nandx, 0x7C0003B8, X)(PPCHIRBuilder& f, InstrData& i) { // RA <- ¬((RS) & (RB)) - Value* ra = f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB)); - ra = f.Not(ra); + Value* ra = f.Not(f.And(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB))); f.StoreGPR(i.X.RA, ra); if (i.X.Rc) { f.UpdateCR(0, ra); diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.bin b/src/alloy/frontend/ppc/test/bin/instr_fsel.bin new file mode 100644 index 0000000000000000000000000000000000000000..ba21487fc427cfc6564874d466ee8628738d62bf GIT binary patch literal 24 ScmeyPr0~wKfkEL98Vvw_tO-v5 literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.dis b/src/alloy/frontend/ppc/test/bin/instr_fsel.dis new file mode 100644 index 000000000..b2ac1fd55 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_fsel.dis @@ -0,0 +1,17 @@ + +/vagrant/src/alloy/frontend/ppc/test/bin//instr_fsel.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: fc 22 20 ee fsel f1,f2,f3,f4 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: fc 22 20 ee fsel f1,f2,f3,f4 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: fc 22 20 ee fsel f1,f2,f3,f4 + 100014: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_fsel.map b/src/alloy/frontend/ppc/test/bin/instr_fsel.map new file mode 100644 index 000000000..ccab66f5f --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_fsel.map @@ -0,0 +1,3 @@ +0000000000000000 t test_fsel_1 +0000000000000008 t test_fsel_2 +0000000000000010 t test_fsel_3 diff --git a/src/alloy/frontend/ppc/test/instr_fsel.s b/src/alloy/frontend/ppc/test/instr_fsel.s new file mode 100644 index 000000000..ca9e52b19 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_fsel.s @@ -0,0 +1,32 @@ +test_fsel_1: + #_ REGISTER_IN f2 2.0 + #_ REGISTER_IN f3 3.0 + #_ REGISTER_IN f4 4.0 + fsel f1, f2, f3, f4 + blr + #_ REGISTER_OUT f1 3.0 + #_ REGISTER_OUT f2 2.0 + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f4 4.0 + +test_fsel_2: + #_ REGISTER_IN f2 -2.0 + #_ REGISTER_IN f3 3.0 + #_ REGISTER_IN f4 4.0 + fsel f1, f2, f3, f4 + blr + #_ REGISTER_OUT f1 4.0 + #_ REGISTER_OUT f2 -2.0 + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f4 4.0 + +test_fsel_3: + #_ REGISTER_IN f2 0.0 + #_ REGISTER_IN f3 3.0 + #_ REGISTER_IN f4 4.0 + fsel f1, f2, f3, f4 + blr + #_ REGISTER_OUT f1 3.0 + #_ REGISTER_OUT f2 0.0 + #_ REGISTER_OUT f3 3.0 + #_ REGISTER_OUT f4 4.0