Basic tests for td, tdi, tw, twi.

2015-06-07 12:51:36 -05:00 · 2015-06-07 12:51:36 -05:00 · be7900614b
parent 43b0cd6eae
commit be7900614b
4 changed files with 1788 additions and 0 deletions
--- a/src/xenia/cpu/frontend/test/instr_td.s
+++ b/src/xenia/cpu/frontend/test/instr_td.s
@ -0,0 +1,511 @@
+test_tdlt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlt_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlt_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdle_1_constant:
+  li r3, 24
+  li r4, 16
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdle_2_constant:
+  li r3, 24
+  li r4, 0
+  tdle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdeq_1:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 24
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tdeq_1_constant:
+  li r3, 0
+  li r4, 24
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tdeq_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdeq_2_constant:
+  li r3, 24
+  li r4, 0
+  tdeq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdge_1_constant:
+  li r3, 24
+  li r4, 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdge_2_constant:
+  li r3, 0
+  li r4, 48
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdge_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdge_3_constant:
+  li r3, -1
+  li r4, 0
+  tdge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_1_constant:
+  li r3, 24
+  li r4, 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_2_constant:
+  li r3, 0
+  li r4, 48
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdgt_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdgt_3_constant:
+  li r3, -1
+  li r4, 0
+  tdgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_1_constant:
+  li r3, 24
+  li r4, 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_2_constant:
+  li r3, 0
+  li r4, 48
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdnl_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdnl_3_constant:
+  li r3, -1
+  li r4, 0
+  tdnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_tdne_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 24
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_tdne_1_constant:
+  li r3, 24
+  li r4, 24
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_tdne_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 0
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_tdne_2_constant:
+  li r3, 0
+  li r4, 0
+  tdne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_tdng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdng_1_constant:
+  li r3, 24
+  li r4, 16
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdng_2_constant:
+  li r3, 24
+  li r4, 0
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdng_3:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 -1
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_tdng_3_constant:
+  li r3, 0
+  li r4, -1
+  tdng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_tdllt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdllt_1_constant:
+  li r3, 24
+  li r4, 16
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdllt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdllt_2_constant:
+  li r3, 24
+  li r4, 0
+  tdllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlle_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlle_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlge_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlgt_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_1_constant:
+  li r3, 24
+  li r4, 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlnl_2_constant:
+  li r3, 0
+  li r4, 48
+  tdlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_tdlng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlng_1_constant:
+  li r3, 24
+  li r4, 16
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_tdlng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tdlng_2_constant:
+  li r3, 24
+  li r4, 0
+  tdlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
--- a/src/xenia/cpu/frontend/test/instr_tdi.s
+++ b/src/xenia/cpu/frontend/test/instr_tdi.s
@ -0,0 +1,383 @@
+test_tdlti_1:
+  #_ REGISTER_IN r3 24
+  tdlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_1_constant:
+  li r3, 24
+  tdlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_2:
+  #_ REGISTER_IN r3 24
+  tdlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlti_2_constant:
+  li r3, 24
+  tdlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_1:
+  #_ REGISTER_IN r3 24
+  tdlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_1_constant:
+  li r3, 24
+  tdlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_2:
+  #_ REGISTER_IN r3 24
+  tdlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlei_2_constant:
+  li r3, 24
+  tdlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdeqi_1:
+  #_ REGISTER_IN r3 0
+  tdeqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdeqi_1_constant:
+  li r3, 0
+  tdeqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdeqi_2:
+  #_ REGISTER_IN r3 24
+  tdeqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdeqi_2_constant:
+  li r3, 24
+  tdeqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_1:
+  #_ REGISTER_IN r3 24
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_1_constant:
+  li r3, 24
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgei_2:
+  #_ REGISTER_IN r3 0
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgei_2_constant:
+  li r3, 0
+  tdgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgei_3:
+  #_ REGISTER_IN r3 -1
+  tdgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgei_3_constant:
+  li r3, -1
+  tdgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgti_1:
+  #_ REGISTER_IN r3 24
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgti_1_constant:
+  li r3, 24
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdgti_2:
+  #_ REGISTER_IN r3 0
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgti_2_constant:
+  li r3, 0
+  tdgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdgti_3:
+  #_ REGISTER_IN r3 -1
+  tdgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdgti_3_constant:
+  li r3, -1
+  tdgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnli_1:
+  #_ REGISTER_IN r3 24
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnli_1_constant:
+  li r3, 24
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnli_2:
+  #_ REGISTER_IN r3 0
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnli_2_constant:
+  li r3, 0
+  tdnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnli_3:
+  #_ REGISTER_IN r3 -1
+  tdnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnli_3_constant:
+  li r3, -1
+  tdnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_tdnei_1:
+  #_ REGISTER_IN r3 24
+  tdnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnei_1_constant:
+  li r3, 24
+  tdnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdnei_2:
+  #_ REGISTER_IN r3 0
+  tdnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdnei_2_constant:
+  li r3, 0
+  tdnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdngi_1:
+  #_ REGISTER_IN r3 24
+  tdngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_1_constant:
+  li r3, 24
+  tdngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_2:
+  #_ REGISTER_IN r3 24
+  tdngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_2_constant:
+  li r3, 24
+  tdngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdngi_3:
+  #_ REGISTER_IN r3 0
+  tdngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdngi_3_constant:
+  li r3, 0
+  tdngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdllti_1:
+  #_ REGISTER_IN r3 24
+  tdllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_1_constant:
+  li r3, 24
+  tdllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_2:
+  #_ REGISTER_IN r3 24
+  tdllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllti_2_constant:
+  li r3, 24
+  tdllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_1:
+  #_ REGISTER_IN r3 24
+  tdllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_1_constant:
+  li r3, 24
+  tdllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_2:
+  #_ REGISTER_IN r3 24
+  tdllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdllei_2_constant:
+  li r3, 24
+  tdllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_1:
+  #_ REGISTER_IN r3 24
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_1_constant:
+  li r3, 24
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgei_2:
+  #_ REGISTER_IN r3 0
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgei_2_constant:
+  li r3, 0
+  tdlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgti_1:
+  #_ REGISTER_IN r3 24
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgti_1_constant:
+  li r3, 24
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlgti_2:
+  #_ REGISTER_IN r3 0
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlgti_2_constant:
+  li r3, 0
+  tdlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlnli_1:
+  #_ REGISTER_IN r3 24
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlnli_1_constant:
+  li r3, 24
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlnli_2:
+  #_ REGISTER_IN r3 0
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlnli_2_constant:
+  li r3, 0
+  tdlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tdlngi_1:
+  #_ REGISTER_IN r3 24
+  tdlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_1_constant:
+  li r3, 24
+  tdlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_2:
+  #_ REGISTER_IN r3 24
+  tdlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tdlngi_2_constant:
+  li r3, 24
+  tdlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
--- a/src/xenia/cpu/frontend/test/instr_tw.s
+++ b/src/xenia/cpu/frontend/test/instr_tw.s
@ -0,0 +1,511 @@
+test_twlt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlt_1_constant:
+  li r3, 24
+  li r4, 16
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlt_2_constant:
+  li r3, 24
+  li r4, 0
+  twlt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twle_1_constant:
+  li r3, 24
+  li r4, 16
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twle_2_constant:
+  li r3, 24
+  li r4, 0
+  twle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tweq_1:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 24
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tweq_1_constant:
+  li r3, 0
+  li r4, 24
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 24
+
+test_tweq_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_tweq_2_constant:
+  li r3, 24
+  li r4, 0
+  tweq r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twge_1_constant:
+  li r3, 24
+  li r4, 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twge_2_constant:
+  li r3, 0
+  li r4, 48
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twge_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twge_3_constant:
+  li r3, -1
+  li r4, 0
+  twge r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twgt_1_constant:
+  li r3, 24
+  li r4, 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twgt_2_constant:
+  li r3, 0
+  li r4, 48
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twgt_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twgt_3_constant:
+  li r3, -1
+  li r4, 0
+  twgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twnl_1_constant:
+  li r3, 24
+  li r4, 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twnl_2_constant:
+  li r3, 0
+  li r4, 48
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twnl_3:
+  #_ REGISTER_IN r3 -1
+  #_ REGISTER_IN r4 0
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twnl_3_constant:
+  li r3, -1
+  li r4, 0
+  twnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 -1
+  #_ REGISTER_OUT r4 0
+
+test_twne_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 24
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_twne_1_constant:
+  li r3, 24
+  li r4, 24
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 24
+
+test_twne_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 0
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_twne_2_constant:
+  li r3, 0
+  li r4, 0
+  twne r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+
+test_twng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twng_1_constant:
+  li r3, 24
+  li r4, 16
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twng_2_constant:
+  li r3, 24
+  li r4, 0
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twng_3:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 -1
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_twng_3_constant:
+  li r3, 0
+  li r4, -1
+  twng r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 -1
+
+test_twllt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twllt_1_constant:
+  li r3, 24
+  li r4, 16
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twllt_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twllt_2_constant:
+  li r3, 24
+  li r4, 0
+  twllt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlle_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlle_1_constant:
+  li r3, 24
+  li r4, 16
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlle_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlle_2_constant:
+  li r3, 24
+  li r4, 0
+  twlle r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlge_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlge_1_constant:
+  li r3, 24
+  li r4, 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlge_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlge_2_constant:
+  li r3, 0
+  li r4, 48
+  twlge r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_1_constant:
+  li r3, 24
+  li r4, 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlgt_2_constant:
+  li r3, 0
+  li r4, 48
+  twlgt r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_1_constant:
+  li r3, 24
+  li r4, 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_2:
+  #_ REGISTER_IN r3 0
+  #_ REGISTER_IN r4 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlnl_2_constant:
+  li r3, 0
+  li r4, 48
+  twlnl r3, r4
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 48
+
+test_twlng_1:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 16
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlng_1_constant:
+  li r3, 24
+  li r4, 16
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 16
+
+test_twlng_2:
+  #_ REGISTER_IN r3 24
+  #_ REGISTER_IN r4 0
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
+
+test_twlng_2_constant:
+  li r3, 24
+  li r4, 0
+  twlng r3, r4
+  blr
+  #_ REGISTER_OUT r3 24
+  #_ REGISTER_OUT r4 0
--- a/src/xenia/cpu/frontend/test/instr_twi.s
+++ b/src/xenia/cpu/frontend/test/instr_twi.s
@ -0,0 +1,383 @@
+test_twlti_1:
+  #_ REGISTER_IN r3 24
+  twlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_1_constant:
+  li r3, 24
+  twlti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_2:
+  #_ REGISTER_IN r3 24
+  twlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlti_2_constant:
+  li r3, 24
+  twlti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_1:
+  #_ REGISTER_IN r3 24
+  twlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_1_constant:
+  li r3, 24
+  twlei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_2:
+  #_ REGISTER_IN r3 24
+  twlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlei_2_constant:
+  li r3, 24
+  twlei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tweqi_1:
+  #_ REGISTER_IN r3 0
+  tweqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tweqi_1_constant:
+  li r3, 0
+  tweqi r3, 24
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_tweqi_2:
+  #_ REGISTER_IN r3 24
+  tweqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_tweqi_2_constant:
+  li r3, 24
+  tweqi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_1:
+  #_ REGISTER_IN r3 24
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_1_constant:
+  li r3, 24
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgei_2:
+  #_ REGISTER_IN r3 0
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgei_2_constant:
+  li r3, 0
+  twgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgei_3:
+  #_ REGISTER_IN r3 -1
+  twgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgei_3_constant:
+  li r3, -1
+  twgei r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgti_1:
+  #_ REGISTER_IN r3 24
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgti_1_constant:
+  li r3, 24
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twgti_2:
+  #_ REGISTER_IN r3 0
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgti_2_constant:
+  li r3, 0
+  twgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twgti_3:
+  #_ REGISTER_IN r3 -1
+  twgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twgti_3_constant:
+  li r3, -1
+  twgti r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnli_1:
+  #_ REGISTER_IN r3 24
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnli_1_constant:
+  li r3, 24
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnli_2:
+  #_ REGISTER_IN r3 0
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnli_2_constant:
+  li r3, 0
+  twnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnli_3:
+  #_ REGISTER_IN r3 -1
+  twnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnli_3_constant:
+  li r3, -1
+  twnli r3, 0
+  blr
+  #_ REGISTER_OUT r3 -1
+
+test_twnei_1:
+  #_ REGISTER_IN r3 24
+  twnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnei_1_constant:
+  li r3, 24
+  twnei r3, 24
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twnei_2:
+  #_ REGISTER_IN r3 0
+  twnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twnei_2_constant:
+  li r3, 0
+  twnei r3, 0
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twngi_1:
+  #_ REGISTER_IN r3 24
+  twngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_1_constant:
+  li r3, 24
+  twngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_2:
+  #_ REGISTER_IN r3 24
+  twngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_2_constant:
+  li r3, 24
+  twngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twngi_3:
+  #_ REGISTER_IN r3 0
+  twngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twngi_3_constant:
+  li r3, 0
+  twngi r3, -1
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twllti_1:
+  #_ REGISTER_IN r3 24
+  twllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_1_constant:
+  li r3, 24
+  twllti r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_2:
+  #_ REGISTER_IN r3 24
+  twllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllti_2_constant:
+  li r3, 24
+  twllti r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_1:
+  #_ REGISTER_IN r3 24
+  twllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_1_constant:
+  li r3, 24
+  twllei r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_2:
+  #_ REGISTER_IN r3 24
+  twllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twllei_2_constant:
+  li r3, 24
+  twllei r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_1:
+  #_ REGISTER_IN r3 24
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_1_constant:
+  li r3, 24
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgei_2:
+  #_ REGISTER_IN r3 0
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgei_2_constant:
+  li r3, 0
+  twlgei r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgti_1:
+  #_ REGISTER_IN r3 24
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgti_1_constant:
+  li r3, 24
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlgti_2:
+  #_ REGISTER_IN r3 0
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlgti_2_constant:
+  li r3, 0
+  twlgti r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlnli_1:
+  #_ REGISTER_IN r3 24
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlnli_1_constant:
+  li r3, 24
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlnli_2:
+  #_ REGISTER_IN r3 0
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlnli_2_constant:
+  li r3, 0
+  twlnli r3, 48
+  blr
+  #_ REGISTER_OUT r3 0
+
+test_twlngi_1:
+  #_ REGISTER_IN r3 24
+  twlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_1_constant:
+  li r3, 24
+  twlngi r3, 16
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_2:
+  #_ REGISTER_IN r3 24
+  twlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24
+
+test_twlngi_2_constant:
+  li r3, 24
+  twlngi r3, 0
+  blr
+  #_ REGISTER_OUT r3 24