diff --git a/src/xenia/cpu/frontend/testing/instr_vmrghb.s b/src/xenia/cpu/frontend/testing/instr_vmrghb.s
index a24a98a86..29181437d 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrghb.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrghb.s
@@ -6,3 +6,12 @@ test_vmrghb_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [00100111, 02120313, 04140515, 06160717]
+
+test_vmrghb_2:
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vmrghb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v5 [F000F101, F202F303, F404F505, F606F707]
diff --git a/src/xenia/cpu/frontend/testing/instr_vmrghh.s b/src/xenia/cpu/frontend/testing/instr_vmrghh.s
index 826a11b3a..fd0fe16db 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrghh.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrghh.s
@@ -6,3 +6,21 @@ test_vmrghh_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [00011011, 02031213, 04051415, 06071617]
+
+test_vmrghh_2:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vmrghh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [00000008, 00010009, 0002000A, 0003000B]
+
+test_vmrghh_3:
+  #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+  #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
+  vmrghh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v5 [FFF80000, FFF90001, FFFA0002, FFFB0003]
diff --git a/src/xenia/cpu/frontend/testing/instr_vmrghw.s b/src/xenia/cpu/frontend/testing/instr_vmrghw.s
index 0aa8f1b08..c22b74c15 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrghw.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrghw.s
@@ -6,3 +6,30 @@ test_vmrghw_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [00010203, 10111213, 04050607, 14151617]
+
+test_vmrghw_2:
+  #_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
+  vmrghw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
+  #_ REGISTER_OUT v5 [00000000, 00000004, 00000001, 00000005]
+
+test_vmrghw_3:
+  #_ REGISTER_IN v3 [C0800000, C0400000, C0000000, BF800000]
+  #_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000]
+  vmrghw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0800000, C0400000, C0000000, BF800000]
+  #_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000]
+  #_ REGISTER_OUT v5 [C0800000, 00000000, C0400000, 3F800000]
+
+test_vmrghw_4:
+  #_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
+  vmrghw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_OUT v5 [FFFFFFFC, 00000000, FFFFFFFD, 00000001]
diff --git a/src/xenia/cpu/frontend/testing/instr_vmrglb.s b/src/xenia/cpu/frontend/testing/instr_vmrglb.s
index c21b25283..35c6801f1 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrglb.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrglb.s
@@ -6,3 +6,12 @@ test_vmrglb_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [08180919, 0a1a0b1b, 0c1c0d1d, 0e1e0f1f]
+
+test_vmrglb_2:
+  #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vmrglb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v5 [F808F909, FA0AFB0B, FC0CFD0D, FE0EFF0F]
diff --git a/src/xenia/cpu/frontend/testing/instr_vmrglh.s b/src/xenia/cpu/frontend/testing/instr_vmrglh.s
index 4f1c647df..d5984854f 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrglh.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrglh.s
@@ -6,3 +6,21 @@ test_vmrglh_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [08091819, 0a0b1a1b, 0c0d1c1d, 0e0f1e1f]
+
+test_vmrglh_2:
+  #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
+  vmrglh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
+  #_ REGISTER_OUT v5 [0004000C, 0005000D, 0006000E, 0007000F]
+
+test_vmrglh_3:
+  #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+  #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
+  vmrglh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
+  #_ REGISTER_OUT v5 [FFFC0004, FFFD0005, FFFE0006, FFFF0007]
diff --git a/src/xenia/cpu/frontend/testing/instr_vmrglw.s b/src/xenia/cpu/frontend/testing/instr_vmrglw.s
index 5567e9fe0..6ecfda7e5 100644
--- a/src/xenia/cpu/frontend/testing/instr_vmrglw.s
+++ b/src/xenia/cpu/frontend/testing/instr_vmrglw.s
@@ -6,3 +6,30 @@ test_vmrglw_1:
   #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
   #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
   #_ REGISTER_OUT v5 [08090a0b, 18191a1b, 0c0d0e0f, 1c1d1e1f]
+
+test_vmrglw_2:
+  #_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
+  vmrglw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
+  #_ REGISTER_OUT v5 [00000002, 00000006, 00000003, 00000007]
+
+test_vmrglw_3:
+  #_ REGISTER_IN v3 [C0800000, C0400000, C0000000, BF800000]
+  #_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000]
+  vmrglw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0800000, C0400000, C0000000, BF800000]
+  #_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000]
+  #_ REGISTER_OUT v5 [C0000000, 40000000, BF800000, 40400000]
+
+test_vmrglw_4:
+  #_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
+  vmrglw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
+  #_ REGISTER_OUT v5 [FFFFFFFE, 00000002, FFFFFFFF, 00000003]