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[x64] Swap to using anchor variables instead of dummy function calls

This commit is contained in:
Dr. Chat 2018-11-23 17:24:55 -06:00
parent df964015a4
commit b3d509eb01
6 changed files with 12 additions and 16 deletions
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2
src/xenia/cpu/backend/x64/x64_backend.cc
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@ -82,8 +82,6 @@ bool X64Backend::Initialize(Processor* processor) {
return false; return false;
} }
RegisterSequences();
// Need movbe to do advanced LOAD/STORE tricks. // Need movbe to do advanced LOAD/STORE tricks.
if (FLAGS_enable_haswell_instructions) { if (FLAGS_enable_haswell_instructions) {
machine_info_.supports_extended_load_store = machine_info_.supports_extended_load_store =

2
src/xenia/cpu/backend/x64/x64_seq_control.cc
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@ -19,7 +19,7 @@ namespace cpu {
namespace backend { namespace backend {
namespace x64 { namespace x64 {
void RegisterControl() {} volatile int anchor_control = 0;
// ============================================================================ // ============================================================================
// OPCODE_DEBUG_BREAK // OPCODE_DEBUG_BREAK

2
src/xenia/cpu/backend/x64/x64_seq_memory.cc
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@ -20,7 +20,7 @@ namespace cpu {
namespace backend { namespace backend {
namespace x64 { namespace x64 {
void RegisterMemory() {} volatile int anchor_memory = 0;
// Note: all types are always aligned in the context. // Note: all types are always aligned in the context.
RegExp ComputeContextAddress(X64Emitter& e, const OffsetOp& offset) { RegExp ComputeContextAddress(X64Emitter& e, const OffsetOp& offset) {

2
src/xenia/cpu/backend/x64/x64_seq_vector.cc
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@ -22,7 +22,7 @@ namespace cpu {
namespace backend { namespace backend {
namespace x64 { namespace x64 {
void RegisterVector() {} volatile int anchor_vector = 0;
// ============================================================================ // ============================================================================
// OPCODE_VECTOR_CONVERT_I2F // OPCODE_VECTOR_CONVERT_I2F

14
src/xenia/cpu/backend/x64/x64_sequences.cc
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@ -3057,11 +3057,15 @@ struct SET_ROUNDING_MODE_I32
}; };
EMITTER_OPCODE_TABLE(OPCODE_SET_ROUNDING_MODE, SET_ROUNDING_MODE_I32); EMITTER_OPCODE_TABLE(OPCODE_SET_ROUNDING_MODE, SET_ROUNDING_MODE_I32);
void RegisterSequences() { // Include anchors to other sequence sources so they get included in the build.
RegisterControl(); extern volatile int anchor_control;
RegisterMemory(); static int anchor_control_dest = anchor_control;
RegisterVector();
} extern volatile int anchor_memory;
static int anchor_memory_dest = anchor_memory;
extern volatile int anchor_vector;
static int anchor_vector_dest = anchor_vector;
bool SelectSequence(X64Emitter* e, const Instr* i, const Instr** new_tail) { bool SelectSequence(X64Emitter* e, const Instr* i, const Instr** new_tail) {
const InstrKey key(i); const InstrKey key(i);

6
src/xenia/cpu/backend/x64/x64_sequences.h
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@ -40,12 +40,6 @@ static bool Register() {
#define EMITTER_OPCODE_TABLE(name, ...) \ #define EMITTER_OPCODE_TABLE(name, ...) \
const auto X64_INSTR_##name = Register<__VA_ARGS__>(); const auto X64_INSTR_##name = Register<__VA_ARGS__>();
// Registration functions to force inclusion of several files
void RegisterControl();
void RegisterMemory();
void RegisterVector();
void RegisterSequences();
bool SelectSequence(X64Emitter* e, const hir::Instr* i, bool SelectSequence(X64Emitter* e, const hir::Instr* i,
const hir::Instr** new_tail); const hir::Instr** new_tail);