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[CPU] Typo fix

This commit is contained in:
Margen67 2020-02-29 06:11:31 -08:00 committed by Justin Moore
parent 5558c8aafe
commit b3d1c5982a
3 changed files with 12 additions and 12 deletions
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8
src/xenia/cpu/backend/x64/x64_seq_memory.cc
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@ -1045,12 +1045,12 @@ struct CACHE_CONTROL
static void Emit(X64Emitter& e, const EmitArgType& i) { static void Emit(X64Emitter& e, const EmitArgType& i) {
bool is_clflush = false, is_prefetch = false; bool is_clflush = false, is_prefetch = false;
switch (CacheControlType(i.instr->flags)) { switch (CacheControlType(i.instr->flags)) {
case CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH: case CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH:
case CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE: case CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE:
is_prefetch = true; is_prefetch = true;
break; break;
case CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE: case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE:
case CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH: case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH:
is_clflush = true; is_clflush = true;
break; break;
default: default:

8
src/xenia/cpu/hir/opcodes.h
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@ -40,10 +40,10 @@ enum LoadStoreFlags {
}; };
enum CacheControlType { enum CacheControlType {
CACHE_CONTOROL_TYPE_DATA_TOUCH, CACHE_CONTROL_TYPE_DATA_TOUCH,
CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE, CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE,
CACHE_CONTOROL_TYPE_DATA_STORE, CACHE_CONTROL_TYPE_DATA_STORE,
CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH, CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH,
}; };
enum ArithmeticFlags { enum ArithmeticFlags {

8
src/xenia/cpu/ppc/ppc_emit_memory.cc
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@ -1082,26 +1082,26 @@ int InstrEmit_stfsx(PPCHIRBuilder& f, const InstrData& i) {
int InstrEmit_dcbf(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_dcbf(PPCHIRBuilder& f, const InstrData& i) {
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.CacheControl(ea, 128, f.CacheControl(ea, 128,
CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH); CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH);
return 0; return 0;
} }
int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) {
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.CacheControl(ea, 128, CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE); f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE);
return 0; return 0;
} }
int InstrEmit_dcbt(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_dcbt(PPCHIRBuilder& f, const InstrData& i) {
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.CacheControl(ea, 128, CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH); f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH);
return 0; return 0;
} }
int InstrEmit_dcbtst(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_dcbtst(PPCHIRBuilder& f, const InstrData& i) {
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.CacheControl(ea, 128, f.CacheControl(ea, 128,
CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE); CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE);
return 0; return 0;
} }