diff --git a/src/xenia/cpu/backend/x64/x64_seq_memory.cc b/src/xenia/cpu/backend/x64/x64_seq_memory.cc
index 819285567..f57d8352d 100644
--- a/src/xenia/cpu/backend/x64/x64_seq_memory.cc
+++ b/src/xenia/cpu/backend/x64/x64_seq_memory.cc
@@ -1045,12 +1045,12 @@ struct CACHE_CONTROL
   static void Emit(X64Emitter& e, const EmitArgType& i) {
     bool is_clflush = false, is_prefetch = false;
     switch (CacheControlType(i.instr->flags)) {
-      case CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH:
-      case CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE:
+      case CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH:
+      case CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE:
         is_prefetch = true;
         break;
-      case CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE:
-      case CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH:
+      case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE:
+      case CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH:
         is_clflush = true;
         break;
       default:
diff --git a/src/xenia/cpu/hir/opcodes.h b/src/xenia/cpu/hir/opcodes.h
index d0e29347c..488e7e168 100644
--- a/src/xenia/cpu/hir/opcodes.h
+++ b/src/xenia/cpu/hir/opcodes.h
@@ -40,10 +40,10 @@ enum LoadStoreFlags {
 };
 
 enum CacheControlType {
-  CACHE_CONTOROL_TYPE_DATA_TOUCH,
-  CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE,
-  CACHE_CONTOROL_TYPE_DATA_STORE,
-  CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH,
+  CACHE_CONTROL_TYPE_DATA_TOUCH,
+  CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE,
+  CACHE_CONTROL_TYPE_DATA_STORE,
+  CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH,
 };
 
 enum ArithmeticFlags {
diff --git a/src/xenia/cpu/ppc/ppc_emit_memory.cc b/src/xenia/cpu/ppc/ppc_emit_memory.cc
index b24172579..ee347682c 100644
--- a/src/xenia/cpu/ppc/ppc_emit_memory.cc
+++ b/src/xenia/cpu/ppc/ppc_emit_memory.cc
@@ -1082,26 +1082,26 @@ int InstrEmit_stfsx(PPCHIRBuilder& f, const InstrData& i) {
 int InstrEmit_dcbf(PPCHIRBuilder& f, const InstrData& i) {
   Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
   f.CacheControl(ea, 128,
-                 CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE_AND_FLUSH);
+                 CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE_AND_FLUSH);
   return 0;
 }
 
 int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) {
   Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
-  f.CacheControl(ea, 128, CacheControlType::CACHE_CONTOROL_TYPE_DATA_STORE);
+  f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE);
   return 0;
 }
 
 int InstrEmit_dcbt(PPCHIRBuilder& f, const InstrData& i) {
   Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
-  f.CacheControl(ea, 128, CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH);
+  f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH);
   return 0;
 }
 
 int InstrEmit_dcbtst(PPCHIRBuilder& f, const InstrData& i) {
   Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
   f.CacheControl(ea, 128,
-                 CacheControlType::CACHE_CONTOROL_TYPE_DATA_TOUCH_FOR_STORE);
+                 CacheControlType::CACHE_CONTROL_TYPE_DATA_TOUCH_FOR_STORE);
   return 0;
 }