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Fixing more x64 stuff.

This commit is contained in:
Ben Vanik 2014-02-10 23:48:41 -08:00
parent 74c9df6697
commit b2f886be98
4 changed files with 29 additions and 8 deletions
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23
src/alloy/backend/x64/lowering/lowering_sequences.cc
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@ -3206,17 +3206,36 @@ table->AddSequence(OPCODE_COMPARE_EXCHANGE, [](X64Emitter& e, Instr*& i) {
}); });
table->AddSequence(OPCODE_ATOMIC_EXCHANGE, [](X64Emitter& e, Instr*& i) { table->AddSequence(OPCODE_ATOMIC_EXCHANGE, [](X64Emitter& e, Instr*& i) {
if (i->dest->type == INT32_TYPE) {
// dest = old_value = InterlockedExchange(src1 = address, src2 = new_value); // dest = old_value = InterlockedExchange(src1 = address, src2 = new_value);
if (i->Match(SIG_TYPE_I32, SIG_TYPE_I64, SIG_TYPE_I32)) {
Reg32 dest, src2; Reg32 dest, src2;
Reg64 src1; Reg64 src1;
e.BeginOp(i->dest, dest, REG_DEST, e.BeginOp(i->dest, dest, REG_DEST,
i->src1.value, src1, 0, i->src1.value, src1, 0,
i->src2.value, src2, 0); i->src2.value, src2, 0);
Reg64 real_src1 = src1;
if (dest.getIdx() == src1.getIdx()) {
e.mov(TEMP_REG, src1);
real_src1 = TEMP_REG;
}
e.mov(dest, src2); e.mov(dest, src2);
e.lock(); e.lock();
e.xchg(e.dword[src1], dest); e.xchg(e.dword[real_src1], dest);
e.EndOp(dest, src1, src2); e.EndOp(dest, src1, src2);
} else if (i->Match(SIG_TYPE_I32, SIG_TYPE_I64, SIG_TYPE_I32C)) {
Reg32 dest;
Reg64 src1;
e.BeginOp(i->dest, dest, REG_DEST,
i->src1.value, src1, 0);
Reg64 real_src1 = src1;
if (dest.getIdx() == src1.getIdx()) {
e.mov(TEMP_REG, src1);
real_src1 = TEMP_REG;
}
e.mov(dest, i->src2.value->constant.i32);
e.lock();
e.xchg(e.dword[real_src1], dest);
e.EndOp(dest, src1);
} else { } else {
ASSERT_INVALID_TYPE(); ASSERT_INVALID_TYPE();
} }

4
src/alloy/backend/x64/lowering/op_utils.inl
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@ -1034,7 +1034,9 @@ void XmmTernaryOpVVV(X64Emitter& e, Instr*& i, xmm_vvv_fn vvv_fn,
if (i->opcode->flags & OPCODE_FLAG_COMMUNATIVE) { if (i->opcode->flags & OPCODE_FLAG_COMMUNATIVE) {
vvv_fn(e, *i, dest, src1, src2); vvv_fn(e, *i, dest, src1, src2);
} else { } else {
UNIMPLEMENTED_SEQ(); e.movaps(e.xmm0, src3);
e.movaps(dest, src1);
vvv_fn(e, *i, dest, src2, e.xmm0);
} }
} else { } else {
e.movaps(dest, src1); e.movaps(dest, src1);

2
src/alloy/backend/x64/x64_emitter.cc
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@ -42,7 +42,7 @@ const uint32_t X64Emitter::gpr_reg_map_[X64Emitter::GPR_COUNT] = {
}; };
const uint32_t X64Emitter::xmm_reg_map_[X64Emitter::XMM_COUNT] = { const uint32_t X64Emitter::xmm_reg_map_[X64Emitter::XMM_COUNT] = {
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
}; };

6
src/alloy/backend/x64/x64_emitter.h
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@ -98,10 +98,10 @@ public:
// Reserved: rsp // Reserved: rsp
// Scratch: rax/rcx/rdx // Scratch: rax/rcx/rdx
// xmm0-1 // xmm0-1
// Available: rbx, r12-r15 (maybe r8-r11, rbp, rsi, rdi?) // Available: rbx, r12-r15 (save to get r8-r11, rbp, rsi, rdi?)
// xmm2-xmm15 // xmm6-xmm15 (save to get xmm2-xmm5)
static const int GPR_COUNT = 5; static const int GPR_COUNT = 5;
static const int XMM_COUNT = 14; static const int XMM_COUNT = 10;
static void SetupReg(hir::Value* v, Xbyak::Reg8& r) { static void SetupReg(hir::Value* v, Xbyak::Reg8& r) {
auto idx = gpr_reg_map_[v->reg.index]; auto idx = gpr_reg_map_[v->reg.index];