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That was a terrible idea. Let us never speak of it again.

This commit is contained in:
Ben Vanik 2014-02-01 00:41:36 -08:00
parent f524693dbb
commit b1ab2fb0a7
4 changed files with 41 additions and 18 deletions
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24
src/alloy/backend/ivm/ivm_intcode.cc
View File

@ -207,21 +207,21 @@ uint32_t IntCode_LOAD_REGISTER_I16(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src2_reg | ((uint64_t)i->src3_reg << 32)); (i->src2_reg | ((uint64_t)i->src3_reg << 32));
ics.rf[i->dest_reg].i16 = (int16_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i16 = XESWAP16((int16_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_LOAD_REGISTER_I32(IntCodeState& ics, const IntCode* i) { uint32_t IntCode_LOAD_REGISTER_I32(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src2_reg | ((uint64_t)i->src3_reg << 32)); (i->src2_reg | ((uint64_t)i->src3_reg << 32));
ics.rf[i->dest_reg].i32 = (int32_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i32 = XESWAP32((int32_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_LOAD_REGISTER_I64(IntCodeState& ics, const IntCode* i) { uint32_t IntCode_LOAD_REGISTER_I64(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src2_reg | ((uint64_t)i->src3_reg << 32)); (i->src2_reg | ((uint64_t)i->src3_reg << 32));
ics.rf[i->dest_reg].i64 = (int64_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i64 = XESWAP64((int64_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
int DispatchRegisterRead( int DispatchRegisterRead(
@ -267,7 +267,7 @@ uint32_t IntCode_LOAD_REGISTER_I16_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
ics.rf[i->dest_reg].i16 = (int16_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i16 = XESWAP16((int16_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;
@ -279,7 +279,7 @@ uint32_t IntCode_LOAD_REGISTER_I32_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
ics.rf[i->dest_reg].i32 = (int32_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i32 = XESWAP32((int32_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;
@ -291,7 +291,7 @@ uint32_t IntCode_LOAD_REGISTER_I64_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
ics.rf[i->dest_reg].i64 = (int64_t)cbs->read(cbs->context, address); ics.rf[i->dest_reg].i64 = XESWAP64((int64_t)cbs->read(cbs->context, address));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;
@ -310,21 +310,21 @@ uint32_t IntCode_STORE_REGISTER_I16(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src3_reg | ((uint64_t)i->dest_reg << 32)); (i->src3_reg | ((uint64_t)i->dest_reg << 32));
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i16); cbs->write(cbs->context, address, XESWAP16(ics.rf[i->src2_reg].i16));
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_STORE_REGISTER_I32(IntCodeState& ics, const IntCode* i) { uint32_t IntCode_STORE_REGISTER_I32(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src3_reg | ((uint64_t)i->dest_reg << 32)); (i->src3_reg | ((uint64_t)i->dest_reg << 32));
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i32); cbs->write(cbs->context, address, XESWAP32(ics.rf[i->src2_reg].i32));
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_STORE_REGISTER_I64(IntCodeState& ics, const IntCode* i) { uint32_t IntCode_STORE_REGISTER_I64(IntCodeState& ics, const IntCode* i) {
uint64_t address = ics.rf[i->src1_reg].u32; uint64_t address = ics.rf[i->src1_reg].u32;
RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*)
(i->src3_reg | ((uint64_t)i->dest_reg << 32)); (i->src3_reg | ((uint64_t)i->dest_reg << 32));
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64); cbs->write(cbs->context, address, XESWAP64(ics.rf[i->src2_reg].i64));
return IA_NEXT; return IA_NEXT;
} }
int DispatchRegisterWrite( int DispatchRegisterWrite(
@ -370,7 +370,7 @@ uint32_t IntCode_STORE_REGISTER_I16_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i16); cbs->write(cbs->context, address, XESWAP16(ics.rf[i->src2_reg].i16));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;
@ -382,7 +382,7 @@ uint32_t IntCode_STORE_REGISTER_I32_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i32); cbs->write(cbs->context, address, XESWAP32(ics.rf[i->src2_reg].i32));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;
@ -394,7 +394,7 @@ uint32_t IntCode_STORE_REGISTER_I64_DYNAMIC(IntCodeState& ics, const IntCode* i)
RegisterAccessCallbacks* cbs = ics.access_callbacks; RegisterAccessCallbacks* cbs = ics.access_callbacks;
while (cbs) { while (cbs) {
if (cbs->handles(cbs->context, address)) { if (cbs->handles(cbs->context, address)) {
cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64); cbs->write(cbs->context, address, XESWAP64(ics.rf[i->src2_reg].i64));
return IA_NEXT; return IA_NEXT;
} }
cbs = cbs->next; cbs = cbs->next;

29
src/alloy/backend/x64/lowering/lowering_sequences.cc
View File

@ -1055,6 +1055,20 @@ table->AddSequence(OPCODE_LOAD, [](X64Emitter& e, Instr*& i) {
e.mov(e.rcx, (uint64_t)cbs->context); e.mov(e.rcx, (uint64_t)cbs->context);
e.mov(e.rdx, i.src1.value->AsUint64()); e.mov(e.rdx, i.src1.value->AsUint64());
CallNative(e, cbs->read); CallNative(e, cbs->read);
switch (i.dest->type) {
case INT8_TYPE:
break;
case INT16_TYPE:
e.xchg(e.al, e.ah);
break;
case INT32_TYPE:
e.bswap(e.eax);
break;
case INT64_TYPE:
e.bswap(e.rax);
break;
default: ASSERT_INVALID_TYPE(); break;
}
e.mov(dest_src, e.rax); e.mov(dest_src, e.rax);
}); });
i = e.Advance(i); i = e.Advance(i);
@ -1092,12 +1106,15 @@ table->AddSequence(OPCODE_LOAD, [](X64Emitter& e, Instr*& i) {
e.movzx(dyn_dest, e.al); e.movzx(dyn_dest, e.al);
break; break;
case INT16_TYPE: case INT16_TYPE:
e.xchg(e.al, e.ah);
e.movzx(dyn_dest, e.ax); e.movzx(dyn_dest, e.ax);
break; break;
case INT32_TYPE: case INT32_TYPE:
e.bswap(e.eax);
e.mov(dyn_dest.cvt32(), e.eax); e.mov(dyn_dest.cvt32(), e.eax);
break; break;
case INT64_TYPE: case INT64_TYPE:
e.bswap(e.rax);
e.mov(dyn_dest, e.rax); e.mov(dyn_dest, e.rax);
break; break;
default: default:
@ -1217,13 +1234,17 @@ table->AddSequence(OPCODE_STORE, [](X64Emitter& e, Instr*& i) {
e.movzx(e.r8d, src2.cvt8()); e.movzx(e.r8d, src2.cvt8());
break; break;
case INT16_TYPE: case INT16_TYPE:
e.movzx(e.r8d, src2.cvt16()); e.movzx(e.rax, src2.cvt16());
e.xchg(e.al, e.ah);
e.mov(e.r8, e.rax);
break; break;
case INT32_TYPE: case INT32_TYPE:
e.movzx(e.r8, src2.cvt32()); e.movzx(e.r8, src2.cvt32());
e.bswap(e.r8d);
break; break;
case INT64_TYPE: case INT64_TYPE:
e.mov(e.r8, src2); e.mov(e.r8, src2);
e.bswap(e.r8);
break; break;
default: ASSERT_INVALID_TYPE(); break; default: ASSERT_INVALID_TYPE(); break;
} }
@ -1263,13 +1284,17 @@ table->AddSequence(OPCODE_STORE, [](X64Emitter& e, Instr*& i) {
e.movzx(e.r8, dyn_src.cvt8()); e.movzx(e.r8, dyn_src.cvt8());
break; break;
case INT16_TYPE: case INT16_TYPE:
e.movzx(e.r8, dyn_src.cvt16()); e.movzx(e.rax, dyn_src.cvt16());
e.xchg(e.al, e.ah);
e.mov(e.r8, e.rax);
break; break;
case INT32_TYPE: case INT32_TYPE:
e.mov(e.r8d, dyn_src.cvt32()); e.mov(e.r8d, dyn_src.cvt32());
e.bswap(e.r8d);
break; break;
case INT64_TYPE: case INT64_TYPE:
e.mov(e.r8, dyn_src); e.mov(e.r8, dyn_src);
e.bswap(e.r8);
break; break;
default: default:
e.db(0xCC); e.db(0xCC);

3
src/xenia/apu/audio_system.cc
View File

@ -187,11 +187,10 @@ uint64_t AudioSystem::ReadRegister(uint64_t addr) {
XELOGAPU("ReadRegister(%.4X)", r); XELOGAPU("ReadRegister(%.4X)", r);
// 1800h is read on startup and stored -- context? buffers? // 1800h is read on startup and stored -- context? buffers?
// 1818h is read during a lock? // 1818h is read during a lock?
return XESWAP32BE(0); return 0;
} }
void AudioSystem::WriteRegister(uint64_t addr, uint64_t value) { void AudioSystem::WriteRegister(uint64_t addr, uint64_t value) {
value = XESWAP32BE((uint32_t)value);
uint32_t r = addr & 0xFFFF; uint32_t r = addr & 0xFFFF;
XELOGAPU("WriteRegister(%.4X, %.8X)", r, value); XELOGAPU("WriteRegister(%.4X, %.8X)", r, value);
// 1804h is written to with 0x02000000 and 0x03000000 around a lock operation // 1804h is written to with 0x02000000 and 0x03000000 around a lock operation

3
src/xenia/gpu/graphics_system.cc
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@ -152,11 +152,10 @@ uint64_t GraphicsSystem::ReadRegister(uint64_t addr) {
} }
XEASSERT(r >= 0 && r < kXEGpuRegisterCount); XEASSERT(r >= 0 && r < kXEGpuRegisterCount);
return XESWAP32BE(regs->values[r].u32); return regs->values[r].u32;
} }
void GraphicsSystem::WriteRegister(uint64_t addr, uint64_t value) { void GraphicsSystem::WriteRegister(uint64_t addr, uint64_t value) {
value = XESWAP32BE((uint32_t)value);
uint32_t r = addr & 0xFFFF; uint32_t r = addr & 0xFFFF;
XELOGGPU("WriteRegister(%.4X, %.8X)", r, value); XELOGGPU("WriteRegister(%.4X, %.8X)", r, value);