From ae02dc7ebac161f4c7edffd13e2706501207e9af Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sun, 2 Feb 2014 01:51:38 -0800
Subject: [PATCH] Fixing rdx clobber from mul/div.

---
 src/alloy/backend/x64/lowering/lowering_sequences.cc | 6 ++++++
 src/alloy/backend/x64/lowering/op_utils.inl          | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/src/alloy/backend/x64/lowering/lowering_sequences.cc b/src/alloy/backend/x64/lowering/lowering_sequences.cc
index d779d731c..2607c4495 100644
--- a/src/alloy/backend/x64/lowering/lowering_sequences.cc
+++ b/src/alloy/backend/x64/lowering/lowering_sequences.cc
@@ -1994,6 +1994,7 @@ table->AddSequence(OPCODE_MUL, [](X64Emitter& e, Instr*& i) {
         e.imul(src);
       }
       e.mov(dest_src, Nax);
+      ReloadRDX(e);
     }, [](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
       // RAX = value, RDX = clobbered
       // TODO(benvanik): make the register allocator put dest_src in RAX?
@@ -2007,6 +2008,7 @@ table->AddSequence(OPCODE_MUL, [](X64Emitter& e, Instr*& i) {
         e.imul(Ndx);
       }
       e.mov(dest_src, Nax);
+      ReloadRDX(e);
     });
   } else if (IsFloatType(i->dest->type)) {
     XmmBinaryOp(e, i, i->flags, [](X64Emitter& e, Instr& i, const Xmm& dest_src, const Xmm& src) {
@@ -2043,6 +2045,7 @@ table->AddSequence(OPCODE_MUL_HI, [](X64Emitter& e, Instr*& i) {
         e.imul(src);
       }
       e.mov(dest_src, Ndx);
+      ReloadRDX(e);
     }, [](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
       // RAX = value, RDX = clobbered
       // TODO(benvanik): make the register allocator put dest_src in RAX?
@@ -2056,6 +2059,7 @@ table->AddSequence(OPCODE_MUL_HI, [](X64Emitter& e, Instr*& i) {
         e.imul(Ndx);
       }
       e.mov(dest_src, Ndx);
+      ReloadRDX(e);
     });
   } else {
     UNIMPLEMENTED_SEQ();
@@ -2077,6 +2081,7 @@ table->AddSequence(OPCODE_DIV, [](X64Emitter& e, Instr*& i) {
         e.idiv(src);
       }
       e.mov(dest_src, Nax);
+      ReloadRDX(e);
     }, [](X64Emitter& e, Instr& i, const Reg& dest_src, uint32_t src) {
       // RAX = value, RDX = clobbered
       // TODO(benvanik): make the register allocator put dest_src in RAX?
@@ -2090,6 +2095,7 @@ table->AddSequence(OPCODE_DIV, [](X64Emitter& e, Instr*& i) {
         e.idiv(Ndx);
       }
       e.mov(dest_src, Nax);
+      ReloadRDX(e);
     });
   } else if (IsFloatType(i->dest->type)) {
     XmmBinaryOp(e, i, i->flags, [](X64Emitter& e, Instr& i, const Xmm& dest_src, const Xmm& src) {
diff --git a/src/alloy/backend/x64/lowering/op_utils.inl b/src/alloy/backend/x64/lowering/op_utils.inl
index ef0be4ab1..da28030c5 100644
--- a/src/alloy/backend/x64/lowering/op_utils.inl
+++ b/src/alloy/backend/x64/lowering/op_utils.inl
@@ -73,6 +73,10 @@ void CallNative(X64Emitter& e, void* target) {
   e.mov(e.rdx, e.qword[e.rcx + 8]); // membase
 }
 
+void ReloadRDX(X64Emitter& e) {
+  e.mov(e.rdx, e.qword[e.rcx + 8]); // membase
+}
+
 // Sets EFLAGs with zf for the given value.
 // ZF = 1 if false, 0 = true (so jz = jump if false)
 void CheckBoolean(X64Emitter& e, Value* v) {