vsplt[bhw] tests.

src/alloy/frontend/ppc/test/bin/instr_vspltb.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltb.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vspltb_1>:
+  100000:	10 60 22 0c 	vspltb  v3,v4,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vspltb_2>:
+  100008:	10 61 22 0c 	vspltb  v3,v4,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vspltb_3>:
+  100010:	10 6f 22 0c 	vspltb  v3,v4,15
+  100014:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vspltb.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_vspltb_1
+0000000000000008 t test_vspltb_2
+0000000000000010 t test_vspltb_3

src/alloy/frontend/ppc/test/bin/instr_vsplth.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsplth.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vsplth_1>:
+  100000:	10 60 22 4c 	vsplth  v3,v4,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vsplth_2>:
+  100008:	10 61 22 4c 	vsplth  v3,v4,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vsplth_3>:
+  100010:	10 67 22 4c 	vsplth  v3,v4,7
+  100014:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vsplth.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_vsplth_1
+0000000000000008 t test_vsplth_2
+0000000000000010 t test_vsplth_3

src/alloy/frontend/ppc/test/bin/instr_vspltw.dis

@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vspltw_1>:
+  100000:	10 60 22 8c 	vspltw  v3,v4,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vspltw_2>:
+  100008:	10 61 22 8c 	vspltw  v3,v4,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vspltw_3>:
+  100010:	10 63 22 8c 	vspltw  v3,v4,3
+  100014:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vspltw.map

@@ -0,0 +1,3 @@
+0000000000000000 t test_vspltw_1
+0000000000000008 t test_vspltw_2
+0000000000000010 t test_vspltw_3

src/alloy/frontend/ppc/test/instr_vspltb.s

@@ -0,0 +1,20 @@
+test_vspltb_1:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltb v3, v4, 0
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vspltb_2:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltb v3, v4, 1
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vspltb_3:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltb v3, v4, 0xF
+  blr
+  #_ REGISTER_OUT v3 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]

src/alloy/frontend/ppc/test/instr_vsplth.s

@@ -0,0 +1,20 @@
+test_vsplth_1:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vsplth v3, v4, 0
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vsplth_2:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vsplth v3, v4, 1
+  blr
+  #_ REGISTER_OUT v3 [02030203, 02030203, 02030203, 02030203]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vsplth_3:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vsplth v3, v4, 7
+  blr
+  #_ REGISTER_OUT v3 [0E0F0E0F, 0E0F0E0F, 0E0F0E0F, 0E0F0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]

src/alloy/frontend/ppc/test/instr_vspltw.s

@@ -0,0 +1,20 @@
+test_vspltw_1:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltw v3, v4, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 00010203, 00010203, 00010203]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vspltw_2:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltw v3, v4, 1
+  blr
+  #_ REGISTER_OUT v3 [04050607, 04050607, 04050607, 04050607]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vspltw_3:
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vspltw v3, v4, 3
+  blr
+  #_ REGISTER_OUT v3 [0C0D0E0F, 0C0D0E0F, 0C0D0E0F, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]