diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.bin b/src/alloy/frontend/ppc/test/bin/instr_vspltb.bin new file mode 100644 index 000000000..2fa47981d Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vspltb.bin differ diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.dis b/src/alloy/frontend/ppc/test/bin/instr_vspltb.dis new file mode 100644 index 000000000..600912aec --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vspltb.dis @@ -0,0 +1,17 @@ + +/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltb.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 10 60 22 0c vspltb v3,v4,0 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 10 61 22 0c vspltb v3,v4,1 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 10 6f 22 0c vspltb v3,v4,15 + 100014: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltb.map b/src/alloy/frontend/ppc/test/bin/instr_vspltb.map new file mode 100644 index 000000000..1c99d3732 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vspltb.map @@ -0,0 +1,3 @@ +0000000000000000 t test_vspltb_1 +0000000000000008 t test_vspltb_2 +0000000000000010 t test_vspltb_3 diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.bin b/src/alloy/frontend/ppc/test/bin/instr_vsplth.bin new file mode 100644 index 000000000..81692954a Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vsplth.bin differ diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.dis b/src/alloy/frontend/ppc/test/bin/instr_vsplth.dis new file mode 100644 index 000000000..4512df243 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vsplth.dis @@ -0,0 +1,17 @@ + +/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsplth.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 10 60 22 4c vsplth v3,v4,0 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 10 61 22 4c vsplth v3,v4,1 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 10 67 22 4c vsplth v3,v4,7 + 100014: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsplth.map b/src/alloy/frontend/ppc/test/bin/instr_vsplth.map new file mode 100644 index 000000000..68f48827f --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vsplth.map @@ -0,0 +1,3 @@ +0000000000000000 t test_vsplth_1 +0000000000000008 t test_vsplth_2 +0000000000000010 t test_vsplth_3 diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.bin b/src/alloy/frontend/ppc/test/bin/instr_vspltw.bin new file mode 100644 index 000000000..d100e823d Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vspltw.bin differ diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.dis b/src/alloy/frontend/ppc/test/bin/instr_vspltw.dis new file mode 100644 index 000000000..147037bae --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vspltw.dis @@ -0,0 +1,17 @@ + +/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltw.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 10 60 22 8c vspltw v3,v4,0 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 10 61 22 8c vspltw v3,v4,1 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 10 63 22 8c vspltw v3,v4,3 + 100014: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_vspltw.map b/src/alloy/frontend/ppc/test/bin/instr_vspltw.map new file mode 100644 index 000000000..5fd932869 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_vspltw.map @@ -0,0 +1,3 @@ +0000000000000000 t test_vspltw_1 +0000000000000008 t test_vspltw_2 +0000000000000010 t test_vspltw_3 diff --git a/src/alloy/frontend/ppc/test/instr_vspltb.s b/src/alloy/frontend/ppc/test/instr_vspltb.s new file mode 100644 index 000000000..71d2197b3 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_vspltb.s @@ -0,0 +1,20 @@ +test_vspltb_1: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltb v3, v4, 0 + blr + #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vspltb_2: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltb v3, v4, 1 + blr + #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vspltb_3: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltb v3, v4, 0xF + blr + #_ REGISTER_OUT v3 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] diff --git a/src/alloy/frontend/ppc/test/instr_vsplth.s b/src/alloy/frontend/ppc/test/instr_vsplth.s new file mode 100644 index 000000000..a6a382d23 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_vsplth.s @@ -0,0 +1,20 @@ +test_vsplth_1: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vsplth v3, v4, 0 + blr + #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vsplth_2: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vsplth v3, v4, 1 + blr + #_ REGISTER_OUT v3 [02030203, 02030203, 02030203, 02030203] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vsplth_3: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vsplth v3, v4, 7 + blr + #_ REGISTER_OUT v3 [0E0F0E0F, 0E0F0E0F, 0E0F0E0F, 0E0F0E0F] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] diff --git a/src/alloy/frontend/ppc/test/instr_vspltw.s b/src/alloy/frontend/ppc/test/instr_vspltw.s new file mode 100644 index 000000000..d9f30e112 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_vspltw.s @@ -0,0 +1,20 @@ +test_vspltw_1: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltw v3, v4, 0 + blr + #_ REGISTER_OUT v3 [00010203, 00010203, 00010203, 00010203] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vspltw_2: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltw v3, v4, 1 + blr + #_ REGISTER_OUT v3 [04050607, 04050607, 04050607, 04050607] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + +test_vspltw_3: + #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F] + vspltw v3, v4, 3 + blr + #_ REGISTER_OUT v3 [0C0D0E0F, 0C0D0E0F, 0C0D0E0F, 0C0D0E0F] + #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]