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'xb gentest' to generate test binaries on Windows.

This commit is contained in:
Ben Vanik 2015-05-12 21:40:44 -07:00
parent c00ded9fbc
commit a72dc93b92
92 changed files with 1149 additions and 1495 deletions
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3
.gitmodules vendored
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@ -19,3 +19,6 @@
[submodule "third_party/flatbuffers"] [submodule "third_party/flatbuffers"]
path = third_party/flatbuffers path = third_party/flatbuffers
url = https://github.com/google/flatbuffers.git url = https://github.com/google/flatbuffers.git
[submodule "third_party/binutils-ppc-cygwin"]
path = third_party/binutils-ppc-cygwin
url = https://github.com/benvanik/binutils-ppc-cygwin

12
src/xenia/cpu/frontend/test/bin/instr_add.dis
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@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_add.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_add_1>: 0000000000100000 <test_add_1>:
100000: 7d 65 ca 14 add r11,r5,r25 100000: 7d 65 ca 14 add r11,r5,r25
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_add_2>: 0000000000100008 <test_add_2>:
100008: 7d 60 ca 14 add r11,r0,r25 100008: 7d 60 ca 14 add r11,r0,r25
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

34
src/xenia/cpu/frontend/test/bin/instr_addc.dis
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@ -1,30 +1,26 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_addc.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_addc_1>: 0000000000100000 <test_addc_1>:
100000: 7c 64 28 14 addc r3,r4,r5 100000: 7c 64 28 14 addc r3,r4,r5
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_addc_2>: 000000000010000c <test_addc_2>:
10000c: 7c 64 28 14 addc r3,r4,r5 10000c: 7c 64 28 14 addc r3,r4,r5
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_addc_3>: 0000000000100018 <test_addc_3>:
100018: 7c 64 28 14 addc r3,r4,r5 100018: 7c 64 28 14 addc r3,r4,r5
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_addc_4>: 0000000000100024 <test_addc_4>:
100024: 7c 64 28 14 addc r3,r4,r5 100024: 7c 64 28 14 addc r3,r4,r5
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_addc_5>: 0000000000100030 <test_addc_5>:
100030: 7c 64 28 14 addc r3,r4,r5 100030: 7c 64 28 14 addc r3,r4,r5
100034: 7c c0 01 14 adde r6,r0,r0 100034: 7c c0 01 14 adde r6,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr

94
src/xenia/cpu/frontend/test/bin/instr_adde.dis
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@ -1,70 +1,66 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_adde.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_adde_1>: 0000000000100000 <test_adde_1>:
100000: 7c 64 29 14 adde r3,r4,r5 100000: 7c 64 29 14 adde r3,r4,r5
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_adde_2>: 000000000010000c <test_adde_2>:
10000c: 7c 63 1a 78 xor r3,r3,r3 10000c: 7c 63 1a 78 xor r3,r3,r3
100010: 7c 63 18 f8 not r3,r3 100010: 7c 63 18 f8 not r3,r3
100014: 30 63 00 01 addic r3,r3,1 100014: 30 63 00 01 addic r3,r3,1
100018: 7c 64 29 14 adde r3,r4,r5 100018: 7c 64 29 14 adde r3,r4,r5
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_adde_3>: 0000000000100024 <test_adde_3>:
100024: 7c 64 29 14 adde r3,r4,r5 100024: 7c 64 29 14 adde r3,r4,r5
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_adde_4>: 0000000000100030 <test_adde_4>:
100030: 7c 63 1a 78 xor r3,r3,r3 100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3 100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1 100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 64 29 14 adde r3,r4,r5 10003c: 7c 64 29 14 adde r3,r4,r5
100040: 7c c0 01 14 adde r6,r0,r0 100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_adde_5>: 0000000000100048 <test_adde_5>:
100048: 7c 64 29 14 adde r3,r4,r5 100048: 7c 64 29 14 adde r3,r4,r5
10004c: 7c c0 01 14 adde r6,r0,r0 10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr
0000000000100054 <test_adde_6>: 0000000000100054 <test_adde_6>:
100054: 7c 63 1a 78 xor r3,r3,r3 100054: 7c 63 1a 78 xor r3,r3,r3
100058: 7c 63 18 f8 not r3,r3 100058: 7c 63 18 f8 not r3,r3
10005c: 30 63 00 01 addic r3,r3,1 10005c: 30 63 00 01 addic r3,r3,1
100060: 7c 64 29 14 adde r3,r4,r5 100060: 7c 64 29 14 adde r3,r4,r5
100064: 7c c0 01 14 adde r6,r0,r0 100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr 100068: 4e 80 00 20 blr
000000000010006c <test_adde_7>: 000000000010006c <test_adde_7>:
10006c: 7c 64 29 14 adde r3,r4,r5 10006c: 7c 64 29 14 adde r3,r4,r5
100070: 7c c0 01 14 adde r6,r0,r0 100070: 7c c0 01 14 adde r6,r0,r0
100074: 4e 80 00 20 blr 100074: 4e 80 00 20 blr
0000000000100078 <test_adde_8>: 0000000000100078 <test_adde_8>:
100078: 7c 63 1a 78 xor r3,r3,r3 100078: 7c 63 1a 78 xor r3,r3,r3
10007c: 7c 63 18 f8 not r3,r3 10007c: 7c 63 18 f8 not r3,r3
100080: 30 63 00 01 addic r3,r3,1 100080: 30 63 00 01 addic r3,r3,1
100084: 7c 64 29 14 adde r3,r4,r5 100084: 7c 64 29 14 adde r3,r4,r5
100088: 7c c0 01 14 adde r6,r0,r0 100088: 7c c0 01 14 adde r6,r0,r0
10008c: 4e 80 00 20 blr 10008c: 4e 80 00 20 blr
0000000000100090 <test_adde_9>: 0000000000100090 <test_adde_9>:
100090: 7c 64 29 14 adde r3,r4,r5 100090: 7c 64 29 14 adde r3,r4,r5
100094: 7c c0 01 14 adde r6,r0,r0 100094: 7c c0 01 14 adde r6,r0,r0
100098: 4e 80 00 20 blr 100098: 4e 80 00 20 blr
000000000010009c <test_adde_10>: 000000000010009c <test_adde_10>:
10009c: 7c 63 1a 78 xor r3,r3,r3 10009c: 7c 63 1a 78 xor r3,r3,r3
1000a0: 7c 63 18 f8 not r3,r3 1000a0: 7c 63 18 f8 not r3,r3
1000a4: 30 63 00 01 addic r3,r3,1 1000a4: 30 63 00 01 addic r3,r3,1
1000a8: 7c 64 29 14 adde r3,r4,r5 1000a8: 7c 64 29 14 adde r3,r4,r5
1000ac: 7c c0 01 14 adde r6,r0,r0 1000ac: 7c c0 01 14 adde r6,r0,r0
1000b0: 4e 80 00 20 blr 1000b0: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_addic.dis
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@ -1,15 +1,11 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_addic.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_addic_1>: 0000000000100000 <test_addic_1>:
100000: 30 84 00 01 addic r4,r4,1 100000: 30 84 00 01 addic r4,r4,1
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_addic_2>: 000000000010000c <test_addic_2>:
10000c: 30 84 00 01 addic r4,r4,1 10000c: 30 84 00 01 addic r4,r4,1
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

76
src/xenia/cpu/frontend/test/bin/instr_addme.dis
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@ -1,57 +1,53 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_addme.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_addme_1>: 0000000000100000 <test_addme_1>:
100000: 7c 64 01 d4 addme r3,r4 100000: 7c 64 01 d4 addme r3,r4
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_addme_2>: 000000000010000c <test_addme_2>:
10000c: 7c 63 1a 78 xor r3,r3,r3 10000c: 7c 63 1a 78 xor r3,r3,r3
100010: 7c 63 18 f8 not r3,r3 100010: 7c 63 18 f8 not r3,r3
100014: 30 63 00 01 addic r3,r3,1 100014: 30 63 00 01 addic r3,r3,1
100018: 7c 64 01 d4 addme r3,r4 100018: 7c 64 01 d4 addme r3,r4
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_addme_3>: 0000000000100024 <test_addme_3>:
100024: 7c 64 01 d4 addme r3,r4 100024: 7c 64 01 d4 addme r3,r4
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_addme_4>: 0000000000100030 <test_addme_4>:
100030: 7c 63 1a 78 xor r3,r3,r3 100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3 100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1 100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 64 01 d4 addme r3,r4 10003c: 7c 64 01 d4 addme r3,r4
100040: 7c c0 01 14 adde r6,r0,r0 100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_addme_5>: 0000000000100048 <test_addme_5>:
100048: 7c 64 01 d4 addme r3,r4 100048: 7c 64 01 d4 addme r3,r4
10004c: 7c c0 01 14 adde r6,r0,r0 10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr
0000000000100054 <test_addme_6>: 0000000000100054 <test_addme_6>:
100054: 7c 63 1a 78 xor r3,r3,r3 100054: 7c 63 1a 78 xor r3,r3,r3
100058: 7c 63 18 f8 not r3,r3 100058: 7c 63 18 f8 not r3,r3
10005c: 30 63 00 01 addic r3,r3,1 10005c: 30 63 00 01 addic r3,r3,1
100060: 7c 64 01 d4 addme r3,r4 100060: 7c 64 01 d4 addme r3,r4
100064: 7c c0 01 14 adde r6,r0,r0 100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr 100068: 4e 80 00 20 blr
000000000010006c <test_addme_7>: 000000000010006c <test_addme_7>:
10006c: 7c 64 01 d4 addme r3,r4 10006c: 7c 64 01 d4 addme r3,r4
100070: 7c c0 01 14 adde r6,r0,r0 100070: 7c c0 01 14 adde r6,r0,r0
100074: 4e 80 00 20 blr 100074: 4e 80 00 20 blr
0000000000100078 <test_addme_8>: 0000000000100078 <test_addme_8>:
100078: 7c 63 1a 78 xor r3,r3,r3 100078: 7c 63 1a 78 xor r3,r3,r3
10007c: 7c 63 18 f8 not r3,r3 10007c: 7c 63 18 f8 not r3,r3
100080: 30 63 00 01 addic r3,r3,1 100080: 30 63 00 01 addic r3,r3,1
100084: 7c 64 01 d4 addme r3,r4 100084: 7c 64 01 d4 addme r3,r4
100088: 7c c0 01 14 adde r6,r0,r0 100088: 7c c0 01 14 adde r6,r0,r0
10008c: 4e 80 00 20 blr 10008c: 4e 80 00 20 blr

76
src/xenia/cpu/frontend/test/bin/instr_addze.dis
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@ -1,57 +1,53 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_addze.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_addze_1>: 0000000000100000 <test_addze_1>:
100000: 7c 64 01 94 addze r3,r4 100000: 7c 64 01 94 addze r3,r4
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_addze_2>: 000000000010000c <test_addze_2>:
10000c: 7c 63 1a 78 xor r3,r3,r3 10000c: 7c 63 1a 78 xor r3,r3,r3
100010: 7c 63 18 f8 not r3,r3 100010: 7c 63 18 f8 not r3,r3
100014: 30 63 00 01 addic r3,r3,1 100014: 30 63 00 01 addic r3,r3,1
100018: 7c 64 01 94 addze r3,r4 100018: 7c 64 01 94 addze r3,r4
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_addze_3>: 0000000000100024 <test_addze_3>:
100024: 7c 64 01 94 addze r3,r4 100024: 7c 64 01 94 addze r3,r4
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_addze_4>: 0000000000100030 <test_addze_4>:
100030: 7c 63 1a 78 xor r3,r3,r3 100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3 100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1 100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 64 01 94 addze r3,r4 10003c: 7c 64 01 94 addze r3,r4
100040: 7c c0 01 14 adde r6,r0,r0 100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_addze_5>: 0000000000100048 <test_addze_5>:
100048: 7c 64 01 94 addze r3,r4 100048: 7c 64 01 94 addze r3,r4
10004c: 7c c0 01 14 adde r6,r0,r0 10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr
0000000000100054 <test_addze_6>: 0000000000100054 <test_addze_6>:
100054: 7c 63 1a 78 xor r3,r3,r3 100054: 7c 63 1a 78 xor r3,r3,r3
100058: 7c 63 18 f8 not r3,r3 100058: 7c 63 18 f8 not r3,r3
10005c: 30 63 00 01 addic r3,r3,1 10005c: 30 63 00 01 addic r3,r3,1
100060: 7c 64 01 94 addze r3,r4 100060: 7c 64 01 94 addze r3,r4
100064: 7c c0 01 14 adde r6,r0,r0 100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr 100068: 4e 80 00 20 blr
000000000010006c <test_addze_7>: 000000000010006c <test_addze_7>:
10006c: 7c 64 01 94 addze r3,r4 10006c: 7c 64 01 94 addze r3,r4
100070: 7c c0 01 14 adde r6,r0,r0 100070: 7c c0 01 14 adde r6,r0,r0
100074: 4e 80 00 20 blr 100074: 4e 80 00 20 blr
0000000000100078 <test_addze_8>: 0000000000100078 <test_addze_8>:
100078: 7c 63 1a 78 xor r3,r3,r3 100078: 7c 63 1a 78 xor r3,r3,r3
10007c: 7c 63 18 f8 not r3,r3 10007c: 7c 63 18 f8 not r3,r3
100080: 30 63 00 01 addic r3,r3,1 100080: 30 63 00 01 addic r3,r3,1
100084: 7c 64 01 94 addze r3,r4 100084: 7c 64 01 94 addze r3,r4
100088: 7c c0 01 14 adde r6,r0,r0 100088: 7c c0 01 14 adde r6,r0,r0
10008c: 4e 80 00 20 blr 10008c: 4e 80 00 20 blr

50
src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis
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@ -1,44 +1,40 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_cntlzd.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_cntlzd_1>: 0000000000100000 <test_cntlzd_1>:
100000: 7c a6 00 74 cntlzd r6,r5 100000: 7c a6 00 74 cntlzd r6,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_cntlzd_1_constant>: 0000000000100008 <test_cntlzd_1_constant>:
100008: 38 a0 00 00 li r5,0 100008: 38 a0 00 00 li r5,0
10000c: 7c a6 00 74 cntlzd r6,r5 10000c: 7c a6 00 74 cntlzd r6,r5
100010: 4e 80 00 20 blr 100010: 4e 80 00 20 blr
0000000000100014 <test_cntlzd_2>: 0000000000100014 <test_cntlzd_2>:
100014: 7c a6 00 74 cntlzd r6,r5 100014: 7c a6 00 74 cntlzd r6,r5
100018: 4e 80 00 20 blr 100018: 4e 80 00 20 blr
000000000010001c <test_cntlzd_2_constant>: 000000000010001c <test_cntlzd_2_constant>:
10001c: 38 a0 00 01 li r5,1 10001c: 38 a0 00 01 li r5,1
100020: 7c a6 00 74 cntlzd r6,r5 100020: 7c a6 00 74 cntlzd r6,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_cntlzd_3>: 0000000000100028 <test_cntlzd_3>:
100028: 7c a6 00 74 cntlzd r6,r5 100028: 7c a6 00 74 cntlzd r6,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_cntlzd_3_constant>: 0000000000100030 <test_cntlzd_3_constant>:
100030: 38 a0 00 00 li r5,0 100030: 38 a0 00 00 li r5,0
100034: 7c a5 28 f8 not r5,r5 100034: 7c a5 28 f8 not r5,r5
100038: 7c a6 00 74 cntlzd r6,r5 100038: 7c a6 00 74 cntlzd r6,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_cntlzd_4>: 0000000000100040 <test_cntlzd_4>:
100040: 7c a6 00 74 cntlzd r6,r5 100040: 7c a6 00 74 cntlzd r6,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_cntlzd_4_constant>: 0000000000100048 <test_cntlzd_4_constant>:
100048: 38 a0 00 00 li r5,0 100048: 38 a0 00 00 li r5,0
10004c: 7c a5 28 f8 not r5,r5 10004c: 7c a5 28 f8 not r5,r5
100050: 78 a5 f8 42 rldicl r5,r5,63,1 100050: 78 a5 f8 42 rldicl r5,r5,63,1
100054: 7c a6 00 74 cntlzd r6,r5 100054: 7c a6 00 74 cntlzd r6,r5
100058: 4e 80 00 20 blr 100058: 4e 80 00 20 blr

52
src/xenia/cpu/frontend/test/bin/instr_cntlzw.dis
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@ -1,45 +1,41 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_cntlzw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_cntlzw_1>: 0000000000100000 <test_cntlzw_1>:
100000: 7c a6 00 34 cntlzw r6,r5 100000: 7c a6 00 34 cntlzw r6,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_cntlzw_1_constant>: 0000000000100008 <test_cntlzw_1_constant>:
100008: 38 a0 00 00 li r5,0 100008: 38 a0 00 00 li r5,0
10000c: 7c a6 00 34 cntlzw r6,r5 10000c: 7c a6 00 34 cntlzw r6,r5
100010: 4e 80 00 20 blr 100010: 4e 80 00 20 blr
0000000000100014 <test_cntlzw_2>: 0000000000100014 <test_cntlzw_2>:
100014: 7c a6 00 34 cntlzw r6,r5 100014: 7c a6 00 34 cntlzw r6,r5
100018: 4e 80 00 20 blr 100018: 4e 80 00 20 blr
000000000010001c <test_cntlzw_2_constant>: 000000000010001c <test_cntlzw_2_constant>:
10001c: 38 a0 00 01 li r5,1 10001c: 38 a0 00 01 li r5,1
100020: 7c a6 00 34 cntlzw r6,r5 100020: 7c a6 00 34 cntlzw r6,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_cntlzw_3>: 0000000000100028 <test_cntlzw_3>:
100028: 7c a6 00 34 cntlzw r6,r5 100028: 7c a6 00 34 cntlzw r6,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_cntlzw_3_constant>: 0000000000100030 <test_cntlzw_3_constant>:
100030: 38 a0 00 00 li r5,0 100030: 38 a0 00 00 li r5,0
100034: 7c a5 28 f8 not r5,r5 100034: 7c a5 28 f8 not r5,r5
100038: 54 a5 00 3e rotlwi r5,r5,0 100038: 54 a5 00 3e rotlwi r5,r5,0
10003c: 7c a6 00 34 cntlzw r6,r5 10003c: 7c a6 00 34 cntlzw r6,r5
100040: 4e 80 00 20 blr 100040: 4e 80 00 20 blr
0000000000100044 <test_cntlzw_4>: 0000000000100044 <test_cntlzw_4>:
100044: 7c a6 00 34 cntlzw r6,r5 100044: 7c a6 00 34 cntlzw r6,r5
100048: 4e 80 00 20 blr 100048: 4e 80 00 20 blr
000000000010004c <test_cntlzw_4_constant>: 000000000010004c <test_cntlzw_4_constant>:
10004c: 38 a0 00 00 li r5,0 10004c: 38 a0 00 00 li r5,0
100050: 7c a5 28 f8 not r5,r5 100050: 7c a5 28 f8 not r5,r5
100054: 54 a5 f8 7e rlwinm r5,r5,31,1,31 100054: 54 a5 f8 7e rlwinm r5,r5,31,1,31
100058: 7c a6 00 34 cntlzw r6,r5 100058: 7c a6 00 34 cntlzw r6,r5
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr

32
src/xenia/cpu/frontend/test/bin/instr_divd.dis
View File

@ -1,33 +1,29 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_divd.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_divd_1>: 0000000000100000 <test_divd_1>:
100000: 7c 64 2b d2 divd r3,r4,r5 100000: 7c 64 2b d2 divd r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_divd_3>: 0000000000100008 <test_divd_3>:
100008: 7c 64 2b d2 divd r3,r4,r5 100008: 7c 64 2b d2 divd r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_divd_4>: 0000000000100010 <test_divd_4>:
100010: 7c 64 2b d2 divd r3,r4,r5 100010: 7c 64 2b d2 divd r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_divd_5>: 0000000000100018 <test_divd_5>:
100018: 7c 64 2b d2 divd r3,r4,r5 100018: 7c 64 2b d2 divd r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_divd_6>: 0000000000100020 <test_divd_6>:
100020: 7c 64 2b d2 divd r3,r4,r5 100020: 7c 64 2b d2 divd r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_divd_7>: 0000000000100028 <test_divd_7>:
100028: 7c 64 2b d2 divd r3,r4,r5 100028: 7c 64 2b d2 divd r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_divd_8>: 0000000000100030 <test_divd_8>:
100030: 7c 64 2b d2 divd r3,r4,r5 100030: 7c 64 2b d2 divd r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr

36
src/xenia/cpu/frontend/test/bin/instr_divdu.dis
View File

@ -1,37 +1,33 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_divdu.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_divdu_1>: 0000000000100000 <test_divdu_1>:
100000: 7c 64 2b 92 divdu r3,r4,r5 100000: 7c 64 2b 92 divdu r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_divdu_3>: 0000000000100008 <test_divdu_3>:
100008: 7c 64 2b 92 divdu r3,r4,r5 100008: 7c 64 2b 92 divdu r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_divdu_4>: 0000000000100010 <test_divdu_4>:
100010: 7c 64 2b 92 divdu r3,r4,r5 100010: 7c 64 2b 92 divdu r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_divdu_5>: 0000000000100018 <test_divdu_5>:
100018: 7c 64 2b 92 divdu r3,r4,r5 100018: 7c 64 2b 92 divdu r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_divdu_6>: 0000000000100020 <test_divdu_6>:
100020: 7c 64 2b 92 divdu r3,r4,r5 100020: 7c 64 2b 92 divdu r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_divdu_7>: 0000000000100028 <test_divdu_7>:
100028: 7c 64 2b 92 divdu r3,r4,r5 100028: 7c 64 2b 92 divdu r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_divdu_8>: 0000000000100030 <test_divdu_8>:
100030: 7c 64 2b 92 divdu r3,r4,r5 100030: 7c 64 2b 92 divdu r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_divdu_9>: 0000000000100038 <test_divdu_9>:
100038: 7c 64 2b 92 divdu r3,r4,r5 100038: 7c 64 2b 92 divdu r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr

44
src/xenia/cpu/frontend/test/bin/instr_divw.dis
View File

@ -1,45 +1,41 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_divw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_divw_1>: 0000000000100000 <test_divw_1>:
100000: 7c 64 2b d6 divw r3,r4,r5 100000: 7c 64 2b d6 divw r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_divw_3>: 0000000000100008 <test_divw_3>:
100008: 7c 64 2b d6 divw r3,r4,r5 100008: 7c 64 2b d6 divw r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_divw_4>: 0000000000100010 <test_divw_4>:
100010: 7c 64 2b d6 divw r3,r4,r5 100010: 7c 64 2b d6 divw r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_divw_5>: 0000000000100018 <test_divw_5>:
100018: 7c 64 2b d6 divw r3,r4,r5 100018: 7c 64 2b d6 divw r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_divw_6>: 0000000000100020 <test_divw_6>:
100020: 7c 64 2b d6 divw r3,r4,r5 100020: 7c 64 2b d6 divw r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_divw_7>: 0000000000100028 <test_divw_7>:
100028: 7c 64 2b d6 divw r3,r4,r5 100028: 7c 64 2b d6 divw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_divw_8>: 0000000000100030 <test_divw_8>:
100030: 7c 64 2b d6 divw r3,r4,r5 100030: 7c 64 2b d6 divw r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_divw_9>: 0000000000100038 <test_divw_9>:
100038: 7c 64 2b d6 divw r3,r4,r5 100038: 7c 64 2b d6 divw r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_divw_10>: 0000000000100040 <test_divw_10>:
100040: 7c 64 2b d6 divw r3,r4,r5 100040: 7c 64 2b d6 divw r3,r4,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_divw_11>: 0000000000100048 <test_divw_11>:
100048: 7c 64 2b d6 divw r3,r4,r5 100048: 7c 64 2b d6 divw r3,r4,r5
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr

48
src/xenia/cpu/frontend/test/bin/instr_divwu.dis
View File

@ -1,49 +1,45 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_divwu.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_divwu_1>: 0000000000100000 <test_divwu_1>:
100000: 7c 64 2b 96 divwu r3,r4,r5 100000: 7c 64 2b 96 divwu r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_divwu_3>: 0000000000100008 <test_divwu_3>:
100008: 7c 64 2b 96 divwu r3,r4,r5 100008: 7c 64 2b 96 divwu r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_divwu_4>: 0000000000100010 <test_divwu_4>:
100010: 7c 64 2b 96 divwu r3,r4,r5 100010: 7c 64 2b 96 divwu r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_divwu_5>: 0000000000100018 <test_divwu_5>:
100018: 7c 64 2b 96 divwu r3,r4,r5 100018: 7c 64 2b 96 divwu r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_divwu_6>: 0000000000100020 <test_divwu_6>:
100020: 7c 64 2b 96 divwu r3,r4,r5 100020: 7c 64 2b 96 divwu r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_divwu_7>: 0000000000100028 <test_divwu_7>:
100028: 7c 64 2b 96 divwu r3,r4,r5 100028: 7c 64 2b 96 divwu r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_divwu_8>: 0000000000100030 <test_divwu_8>:
100030: 7c 64 2b 96 divwu r3,r4,r5 100030: 7c 64 2b 96 divwu r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_divwu_9>: 0000000000100038 <test_divwu_9>:
100038: 7c 64 2b 96 divwu r3,r4,r5 100038: 7c 64 2b 96 divwu r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_divwu_10>: 0000000000100040 <test_divwu_10>:
100040: 7c 64 2b 96 divwu r3,r4,r5 100040: 7c 64 2b 96 divwu r3,r4,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_divwu_11>: 0000000000100048 <test_divwu_11>:
100048: 7c 64 2b 96 divwu r3,r4,r5 100048: 7c 64 2b 96 divwu r3,r4,r5
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr
0000000000100050 <test_divwu_12>: 0000000000100050 <test_divwu_12>:
100050: 7c 64 2b 96 divwu r3,r4,r5 100050: 7c 64 2b 96 divwu r3,r4,r5
100054: 4e 80 00 20 blr 100054: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_eqv.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_eqv.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_eqv_1>: 0000000000100000 <test_eqv_1>:
100000: 7c 83 2a 38 eqv r3,r4,r5 100000: 7c 83 2a 38 eqv r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_eqv_2>: 0000000000100008 <test_eqv_2>:
100008: 7c 83 2a 38 eqv r3,r4,r5 100008: 7c 83 2a 38 eqv r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_eqv_3>: 0000000000100010 <test_eqv_3>:
100010: 7c 83 2a 38 eqv r3,r4,r5 100010: 7c 83 2a 38 eqv r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_eqv_4>: 0000000000100018 <test_eqv_4>:
100018: 7c 83 2a 38 eqv r3,r4,r5 100018: 7c 83 2a 38 eqv r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_eqv_5>: 0000000000100020 <test_eqv_5>:
100020: 7c 83 2a 38 eqv r3,r4,r5 100020: 7c 83 2a 38 eqv r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_eqv_6>: 0000000000100028 <test_eqv_6>:
100028: 7c 83 2a 38 eqv r3,r4,r5 100028: 7c 83 2a 38 eqv r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_fabs.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_fabs.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_fabs_1>: 0000000000100000 <test_fabs_1>:
100000: fc 20 0a 10 fabs f1,f1 100000: fc 20 0a 10 fabs f1,f1
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_fabs_2>: 0000000000100008 <test_fabs_2>:
100008: fc 20 0a 10 fabs f1,f1 100008: fc 20 0a 10 fabs f1,f1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_fabs_3>: 0000000000100010 <test_fabs_3>:
100010: fc 20 0a 10 fabs f1,f1 100010: fc 20 0a 10 fabs f1,f1
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_fnabs.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_fnabs.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_fnabs_1>: 0000000000100000 <test_fnabs_1>:
100000: fc 40 09 10 fnabs f2,f1 100000: fc 40 09 10 fnabs f2,f1
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_fsel.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_fsel.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_fsel_1>: 0000000000100000 <test_fsel_1>:
100000: fc 22 20 ee fsel f1,f2,f3,f4 100000: fc 22 20 ee fsel f1,f2,f3,f4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_fsel_2>: 0000000000100008 <test_fsel_2>:
100008: fc 22 20 ee fsel f1,f2,f3,f4 100008: fc 22 20 ee fsel f1,f2,f3,f4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_fsel_3>: 0000000000100010 <test_fsel_3>:
100010: fc 22 20 ee fsel f1,f2,f3,f4 100010: fc 22 20 ee fsel f1,f2,f3,f4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_lvexx.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvexx.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_lvebx_1>: 0000000000100000 <test_lvebx_1>:
100000: 7c 60 20 0e lvebx v3,0,r4 100000: 7c 60 20 0e lvebx v3,0,r4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_lvebx_2>: 0000000000100008 <test_lvebx_2>:
100008: 7c 60 20 0e lvebx v3,0,r4 100008: 7c 60 20 0e lvebx v3,0,r4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_lvehx_1>: 0000000000100010 <test_lvehx_1>:
100010: 7c 60 20 4e lvehx v3,0,r4 100010: 7c 60 20 4e lvehx v3,0,r4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_lvehx_2>: 0000000000100018 <test_lvehx_2>:
100018: 7c 60 20 4e lvehx v3,0,r4 100018: 7c 60 20 4e lvehx v3,0,r4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_lvewx_1>: 0000000000100020 <test_lvewx_1>:
100020: 7c 60 20 8e lvewx v3,0,r4 100020: 7c 60 20 8e lvewx v3,0,r4
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_lvewx_2>: 0000000000100028 <test_lvewx_2>:
100028: 7c 60 20 8e lvewx v3,0,r4 100028: 7c 60 20 8e lvewx v3,0,r4
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_lvl.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvl.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_lvl_1>: 0000000000100000 <test_lvl_1>:
100000: 7c 64 04 0e lvlx v3,r4,r0 100000: 7c 64 04 0e lvlx v3,r4,r0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_lvr.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvr.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_lvr_1>: 0000000000100000 <test_lvr_1>:
100000: 7c 64 2c 4e lvrx v3,r4,r5 100000: 7c 64 2c 4e lvrx v3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_lvsl.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvsl.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_lvsl_1>: 0000000000100000 <test_lvsl_1>:
100000: 7c 64 00 0c lvsl v3,r4,r0 100000: 7c 64 00 0c lvsl v3,r4,r0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_lvsl_2>: 0000000000100008 <test_lvsl_2>:
100008: 7c 64 00 0c lvsl v3,r4,r0 100008: 7c 64 00 0c lvsl v3,r4,r0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_lvsl_3>: 0000000000100010 <test_lvsl_3>:
100010: 7c 64 00 0c lvsl v3,r4,r0 100010: 7c 64 00 0c lvsl v3,r4,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_lvsr.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_lvsr.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_lvsr_1>: 0000000000100000 <test_lvsr_1>:
100000: 7c 64 00 4c lvsr v3,r4,r0 100000: 7c 64 00 4c lvsr v3,r4,r0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_lvsr_2>: 0000000000100008 <test_lvsr_2>:
100008: 7c 64 00 4c lvsr v3,r4,r0 100008: 7c 64 00 4c lvsr v3,r4,r0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_lvsr_3>: 0000000000100010 <test_lvsr_3>:
100010: 7c 64 00 4c lvsr v3,r4,r0 100010: 7c 64 00 4c lvsr v3,r4,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

24
src/xenia/cpu/frontend/test/bin/instr_mulhd.dis
View File

@ -1,25 +1,21 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhd.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulhd_1>: 0000000000100000 <test_mulhd_1>:
100000: 7c 64 28 92 mulhd r3,r4,r5 100000: 7c 64 28 92 mulhd r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulhd_2>: 0000000000100008 <test_mulhd_2>:
100008: 7c 64 28 92 mulhd r3,r4,r5 100008: 7c 64 28 92 mulhd r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhd_3>: 0000000000100010 <test_mulhd_3>:
100010: 7c 64 28 92 mulhd r3,r4,r5 100010: 7c 64 28 92 mulhd r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulhd_4>: 0000000000100018 <test_mulhd_4>:
100018: 7c 64 28 92 mulhd r3,r4,r5 100018: 7c 64 28 92 mulhd r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhd_5>: 0000000000100020 <test_mulhd_5>:
100020: 7c 64 28 92 mulhd r3,r4,r5 100020: 7c 64 28 92 mulhd r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr

24
src/xenia/cpu/frontend/test/bin/instr_mulhdu.dis
View File

@ -1,25 +1,21 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhdu.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulhdu_1>: 0000000000100000 <test_mulhdu_1>:
100000: 7c 64 28 12 mulhdu r3,r4,r5 100000: 7c 64 28 12 mulhdu r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulhdu_2>: 0000000000100008 <test_mulhdu_2>:
100008: 7c 64 28 12 mulhdu r3,r4,r5 100008: 7c 64 28 12 mulhdu r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhdu_3>: 0000000000100010 <test_mulhdu_3>:
100010: 7c 64 28 12 mulhdu r3,r4,r5 100010: 7c 64 28 12 mulhdu r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulhdu_4>: 0000000000100018 <test_mulhdu_4>:
100018: 7c 64 28 12 mulhdu r3,r4,r5 100018: 7c 64 28 12 mulhdu r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhdu_5>: 0000000000100020 <test_mulhdu_5>:
100020: 7c 64 28 12 mulhdu r3,r4,r5 100020: 7c 64 28 12 mulhdu r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_mulhw.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulhw_1>: 0000000000100000 <test_mulhw_1>:
100000: 7c 64 28 96 mulhw r3,r4,r5 100000: 7c 64 28 96 mulhw r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulhw_2>: 0000000000100008 <test_mulhw_2>:
100008: 7c 64 28 96 mulhw r3,r4,r5 100008: 7c 64 28 96 mulhw r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhw_3>: 0000000000100010 <test_mulhw_3>:
100010: 7c 64 28 96 mulhw r3,r4,r5 100010: 7c 64 28 96 mulhw r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulhw_4>: 0000000000100018 <test_mulhw_4>:
100018: 7c 64 28 96 mulhw r3,r4,r5 100018: 7c 64 28 96 mulhw r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhw_5>: 0000000000100020 <test_mulhw_5>:
100020: 7c 64 28 96 mulhw r3,r4,r5 100020: 7c 64 28 96 mulhw r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_mulhw_6>: 0000000000100028 <test_mulhw_6>:
100028: 7c 64 28 96 mulhw r3,r4,r5 100028: 7c 64 28 96 mulhw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_mulhwu.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulhwu.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulhwu_1>: 0000000000100000 <test_mulhwu_1>:
100000: 7c 64 28 16 mulhwu r3,r4,r5 100000: 7c 64 28 16 mulhwu r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulhwu_2>: 0000000000100008 <test_mulhwu_2>:
100008: 7c 64 28 16 mulhwu r3,r4,r5 100008: 7c 64 28 16 mulhwu r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhwu_3>: 0000000000100010 <test_mulhwu_3>:
100010: 7c 64 28 16 mulhwu r3,r4,r5 100010: 7c 64 28 16 mulhwu r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulhwu_4>: 0000000000100018 <test_mulhwu_4>:
100018: 7c 64 28 16 mulhwu r3,r4,r5 100018: 7c 64 28 16 mulhwu r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhwu_5>: 0000000000100020 <test_mulhwu_5>:
100020: 7c 64 28 16 mulhwu r3,r4,r5 100020: 7c 64 28 16 mulhwu r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_mulhwu_6>: 0000000000100028 <test_mulhwu_6>:
100028: 7c 64 28 16 mulhwu r3,r4,r5 100028: 7c 64 28 16 mulhwu r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

36
src/xenia/cpu/frontend/test/bin/instr_mulld.dis
View File

@ -1,37 +1,33 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulld.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulld_1>: 0000000000100000 <test_mulld_1>:
100000: 7c 64 29 d2 mulld r3,r4,r5 100000: 7c 64 29 d2 mulld r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulld_2>: 0000000000100008 <test_mulld_2>:
100008: 7c 64 29 d2 mulld r3,r4,r5 100008: 7c 64 29 d2 mulld r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulld_3>: 0000000000100010 <test_mulld_3>:
100010: 7c 64 29 d2 mulld r3,r4,r5 100010: 7c 64 29 d2 mulld r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulld_4>: 0000000000100018 <test_mulld_4>:
100018: 7c 64 29 d2 mulld r3,r4,r5 100018: 7c 64 29 d2 mulld r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulld_5>: 0000000000100020 <test_mulld_5>:
100020: 7c 64 29 d2 mulld r3,r4,r5 100020: 7c 64 29 d2 mulld r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_mulld_6>: 0000000000100028 <test_mulld_6>:
100028: 7c 64 29 d2 mulld r3,r4,r5 100028: 7c 64 29 d2 mulld r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_mulld_7>: 0000000000100030 <test_mulld_7>:
100030: 7c 64 29 d2 mulld r3,r4,r5 100030: 7c 64 29 d2 mulld r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_mulld_8>: 0000000000100038 <test_mulld_8>:
100038: 7c 64 29 d2 mulld r3,r4,r5 100038: 7c 64 29 d2 mulld r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr

36
src/xenia/cpu/frontend/test/bin/instr_mulli.dis
View File

@ -1,37 +1,33 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mulli.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mulli_1>: 0000000000100000 <test_mulli_1>:
100000: 1c 64 00 00 mulli r3,r4,0 100000: 1c 64 00 00 mulli r3,r4,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mulli_2>: 0000000000100008 <test_mulli_2>:
100008: 1c 64 00 01 mulli r3,r4,1 100008: 1c 64 00 01 mulli r3,r4,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mulli_3>: 0000000000100010 <test_mulli_3>:
100010: 1c 64 ff ff mulli r3,r4,-1 100010: 1c 64 ff ff mulli r3,r4,-1
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mulli_4>: 0000000000100018 <test_mulli_4>:
100018: 1c 64 ff ff mulli r3,r4,-1 100018: 1c 64 ff ff mulli r3,r4,-1
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mulli_5>: 0000000000100020 <test_mulli_5>:
100020: 1c 64 00 01 mulli r3,r4,1 100020: 1c 64 00 01 mulli r3,r4,1
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_mulli_6>: 0000000000100028 <test_mulli_6>:
100028: 1c 64 00 02 mulli r3,r4,2 100028: 1c 64 00 02 mulli r3,r4,2
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_mulli_7>: 0000000000100030 <test_mulli_7>:
100030: 1c 64 ff ff mulli r3,r4,-1 100030: 1c 64 ff ff mulli r3,r4,-1
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_mulli_8>: 0000000000100038 <test_mulli_8>:
100038: 1c 64 ff ff mulli r3,r4,-1 100038: 1c 64 ff ff mulli r3,r4,-1
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr

48
src/xenia/cpu/frontend/test/bin/instr_mullw.dis
View File

@ -1,49 +1,45 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_mullw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_mullw_1>: 0000000000100000 <test_mullw_1>:
100000: 7c 64 29 d6 mullw r3,r4,r5 100000: 7c 64 29 d6 mullw r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_mullw_2>: 0000000000100008 <test_mullw_2>:
100008: 7c 64 29 d6 mullw r3,r4,r5 100008: 7c 64 29 d6 mullw r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_mullw_3>: 0000000000100010 <test_mullw_3>:
100010: 7c 64 29 d6 mullw r3,r4,r5 100010: 7c 64 29 d6 mullw r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_mullw_4>: 0000000000100018 <test_mullw_4>:
100018: 7c 64 29 d6 mullw r3,r4,r5 100018: 7c 64 29 d6 mullw r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_mullw_5>: 0000000000100020 <test_mullw_5>:
100020: 7c 64 29 d6 mullw r3,r4,r5 100020: 7c 64 29 d6 mullw r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_mullw_6>: 0000000000100028 <test_mullw_6>:
100028: 7c 64 29 d6 mullw r3,r4,r5 100028: 7c 64 29 d6 mullw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_mullw_7>: 0000000000100030 <test_mullw_7>:
100030: 7c 64 29 d6 mullw r3,r4,r5 100030: 7c 64 29 d6 mullw r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_mullw_8>: 0000000000100038 <test_mullw_8>:
100038: 7c 64 29 d6 mullw r3,r4,r5 100038: 7c 64 29 d6 mullw r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_mullw_9>: 0000000000100040 <test_mullw_9>:
100040: 7c 64 29 d6 mullw r3,r4,r5 100040: 7c 64 29 d6 mullw r3,r4,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_mullw_10>: 0000000000100048 <test_mullw_10>:
100048: 7c 64 29 d6 mullw r3,r4,r5 100048: 7c 64 29 d6 mullw r3,r4,r5
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr
0000000000100050 <test_mullw_11>: 0000000000100050 <test_mullw_11>:
100050: 7c 64 29 d6 mullw r3,r4,r5 100050: 7c 64 29 d6 mullw r3,r4,r5
100054: 4e 80 00 20 blr 100054: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_neg.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_neg.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_neg_1>: 0000000000100000 <test_neg_1>:
100000: 7c 63 00 d0 neg r3,r3 100000: 7c 63 00 d0 neg r3,r3
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_neg_2>: 0000000000100008 <test_neg_2>:
100008: 7c 63 00 d0 neg r3,r3 100008: 7c 63 00 d0 neg r3,r3
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_neg_3>: 0000000000100010 <test_neg_3>:
100010: 7c 63 00 d0 neg r3,r3 100010: 7c 63 00 d0 neg r3,r3
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

14
src/xenia/cpu/frontend/test/bin/instr_nor.dis
View File

@ -1,14 +1,10 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_nor.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_nor_cr_1>: 0000000000100000 <test_nor_cr_1>:
100000: 7c 63 18 f9 not. r3,r3 100000: 7c 63 18 f9 not. r3,r3
100004: 38 60 00 00 li r3,0 100004: 38 60 00 00 li r3,0
100008: 40 82 00 08 bne 100010 <.nor_cr_1_ne> 100008: 40 82 00 08 bne 100010 <.nor_cr_1_ne>
10000c: 38 60 00 01 li r3,1 10000c: 38 60 00 01 li r3,1
0000000000100010 <.nor_cr_1_ne>: 0000000000100010 <.nor_cr_1_ne>:
100010: 4e 80 00 20 blr 100010: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_ori.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_ori.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_ori_1>: 0000000000100000 <test_ori_1>:
100000: 60 83 fe dc ori r3,r4,65244 100000: 60 83 fe dc ori r3,r4,65244
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_ori_2>: 0000000000100008 <test_ori_2>:
100008: 60 83 fe dc ori r3,r4,65244 100008: 60 83 fe dc ori r3,r4,65244
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

68
src/xenia/cpu/frontend/test/bin/instr_rldicl.dis
View File

@ -1,65 +1,61 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_rldicl.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_rldicl_1>: 0000000000100000 <test_rldicl_1>:
100000: 78 83 c0 00 rotldi r3,r4,24 100000: 78 83 c0 00 rotldi r3,r4,24
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_rldicl_2>: 0000000000100008 <test_rldicl_2>:
100008: 78 83 c2 00 rldicl r3,r4,24,8 100008: 78 83 c2 00 rldicl r3,r4,24,8
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_rldicl_3>: 0000000000100010 <test_rldicl_3>:
100010: 78 83 c7 e0 rldicl r3,r4,24,63 100010: 78 83 c7 e0 rldicl r3,r4,24,63
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_rldicl_4>: 0000000000100018 <test_rldicl_4>:
100018: 78 83 00 00 rotldi r3,r4,0 100018: 78 83 00 00 rotldi r3,r4,0
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_rldicl_5>: 0000000000100020 <test_rldicl_5>:
100020: 78 83 07 e0 clrldi r3,r4,63 100020: 78 83 07 e0 clrldi r3,r4,63
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_rldicl_6>: 0000000000100028 <test_rldicl_6>:
100028: 78 83 02 00 clrldi r3,r4,8 100028: 78 83 02 00 clrldi r3,r4,8
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_rldicl_7>: 0000000000100030 <test_rldicl_7>:
100030: 78 83 f8 02 rotldi r3,r4,63 100030: 78 83 f8 02 rotldi r3,r4,63
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_rldicl_8>: 0000000000100038 <test_rldicl_8>:
100038: 78 83 ff e2 rldicl r3,r4,63,63 100038: 78 83 ff e2 rldicl r3,r4,63,63
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_rldicl_9>: 0000000000100040 <test_rldicl_9>:
100040: 78 83 f8 00 rotldi r3,r4,31 100040: 78 83 f8 00 rotldi r3,r4,31
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_rldicl_10>: 0000000000100048 <test_rldicl_10>:
100048: 78 83 d1 82 rldicl r3,r4,58,6 100048: 78 83 d1 82 rldicl r3,r4,58,6
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr
0000000000100050 <test_srdi_1>: 0000000000100050 <test_srdi_1>:
100050: 78 63 00 00 rotldi r3,r3,0 100050: 78 63 00 00 rotldi r3,r3,0
100054: 78 84 00 00 rotldi r4,r4,0 100054: 78 84 00 00 rotldi r4,r4,0
100058: 4e 80 00 20 blr 100058: 4e 80 00 20 blr
000000000010005c <test_srdi_2>: 000000000010005c <test_srdi_2>:
10005c: 78 63 f8 42 rldicl r3,r3,63,1 10005c: 78 63 f8 42 rldicl r3,r3,63,1
100060: 78 84 f8 42 rldicl r4,r4,63,1 100060: 78 84 f8 42 rldicl r4,r4,63,1
100064: 4e 80 00 20 blr 100064: 4e 80 00 20 blr
0000000000100068 <test_srdi_3>: 0000000000100068 <test_srdi_3>:
100068: 78 63 00 22 rldicl r3,r3,32,32 100068: 78 63 00 22 rldicl r3,r3,32,32
10006c: 78 84 00 22 rldicl r4,r4,32,32 10006c: 78 84 00 22 rldicl r4,r4,32,32
100070: 4e 80 00 20 blr 100070: 4e 80 00 20 blr
0000000000100074 <test_srdi_4>: 0000000000100074 <test_srdi_4>:
100074: 78 63 0f e0 rldicl r3,r3,1,63 100074: 78 63 0f e0 rldicl r3,r3,1,63
100078: 78 84 0f e0 rldicl r4,r4,1,63 100078: 78 84 0f e0 rldicl r4,r4,1,63
10007c: 4e 80 00 20 blr 10007c: 4e 80 00 20 blr

64
src/xenia/cpu/frontend/test/bin/instr_rldicr.dis
View File

@ -1,61 +1,57 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_rldicr.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_rldicr_1>: 0000000000100000 <test_rldicr_1>:
100000: 78 83 c0 04 rldicr r3,r4,24,0 100000: 78 83 c0 04 rldicr r3,r4,24,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_rldicr_2>: 0000000000100008 <test_rldicr_2>:
100008: 78 83 c2 04 rldicr r3,r4,24,8 100008: 78 83 c2 04 rldicr r3,r4,24,8
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_rldicr_3>: 0000000000100010 <test_rldicr_3>:
100010: 78 83 c7 e4 rldicr r3,r4,24,63 100010: 78 83 c7 e4 rldicr r3,r4,24,63
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_rldicr_4>: 0000000000100018 <test_rldicr_4>:
100018: 78 83 00 04 rldicr r3,r4,0,0 100018: 78 83 00 04 rldicr r3,r4,0,0
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_rldicr_5>: 0000000000100020 <test_rldicr_5>:
100020: 78 83 07 e4 rldicr r3,r4,0,63 100020: 78 83 07 e4 rldicr r3,r4,0,63
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_rldicr_6>: 0000000000100028 <test_rldicr_6>:
100028: 78 83 02 04 rldicr r3,r4,0,8 100028: 78 83 02 04 rldicr r3,r4,0,8
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_rldicr_7>: 0000000000100030 <test_rldicr_7>:
100030: 78 83 f8 06 rldicr r3,r4,63,0 100030: 78 83 f8 06 rldicr r3,r4,63,0
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_rldicr_8>: 0000000000100038 <test_rldicr_8>:
100038: 78 83 ff e6 rldicr r3,r4,63,63 100038: 78 83 ff e6 rldicr r3,r4,63,63
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_rldicr_9>: 0000000000100040 <test_rldicr_9>:
100040: 78 83 f8 04 rldicr r3,r4,31,0 100040: 78 83 f8 04 rldicr r3,r4,31,0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_sldi_1>: 0000000000100048 <test_sldi_1>:
100048: 78 63 07 e4 rldicr r3,r3,0,63 100048: 78 63 07 e4 rldicr r3,r3,0,63
10004c: 78 84 07 e4 rldicr r4,r4,0,63 10004c: 78 84 07 e4 rldicr r4,r4,0,63
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr
0000000000100054 <test_sldi_2>: 0000000000100054 <test_sldi_2>:
100054: 78 63 0f a4 rldicr r3,r3,1,62 100054: 78 63 0f a4 rldicr r3,r3,1,62
100058: 78 84 0f a4 rldicr r4,r4,1,62 100058: 78 84 0f a4 rldicr r4,r4,1,62
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr
0000000000100060 <test_sldi_3>: 0000000000100060 <test_sldi_3>:
100060: 78 63 07 c6 rldicr r3,r3,32,31 100060: 78 63 07 c6 rldicr r3,r3,32,31
100064: 78 84 07 c6 rldicr r4,r4,32,31 100064: 78 84 07 c6 rldicr r4,r4,32,31
100068: 4e 80 00 20 blr 100068: 4e 80 00 20 blr
000000000010006c <test_sldi_4>: 000000000010006c <test_sldi_4>:
10006c: 78 63 f8 06 rldicr r3,r3,63,0 10006c: 78 63 f8 06 rldicr r3,r3,63,0
100070: 78 84 f8 06 rldicr r4,r4,63,0 100070: 78 84 f8 06 rldicr r4,r4,63,0
100074: 4e 80 00 20 blr 100074: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_rlwimi.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_rlwimi>: 0000000000100000 <test_rlwimi>:
100000: 50 86 10 3a rlwimi r6,r4,2,0,29 100000: 50 86 10 3a rlwimi r6,r4,2,0,29
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

44
src/xenia/cpu/frontend/test/bin/instr_rlwinm.dis
View File

@ -1,45 +1,41 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_rlwinm.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_rlwinm_extrwi>: 0000000000100000 <test_rlwinm_extrwi>:
100000: 54 a7 ef 3e rlwinm r7,r5,29,28,31 100000: 54 a7 ef 3e rlwinm r7,r5,29,28,31
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_rlwinm_1>: 0000000000100008 <test_rlwinm_1>:
100008: 54 83 c2 1e rlwinm r3,r4,24,8,15 100008: 54 83 c2 1e rlwinm r3,r4,24,8,15
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_rlwinm_2>: 0000000000100010 <test_rlwinm_2>:
100010: 54 83 20 36 rlwinm r3,r4,4,0,27 100010: 54 83 20 36 rlwinm r3,r4,4,0,27
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_rlwinm_3>: 0000000000100018 <test_rlwinm_3>:
100018: 54 83 10 3a rlwinm r3,r4,2,0,29 100018: 54 83 10 3a rlwinm r3,r4,2,0,29
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_rlwinm_4>: 0000000000100020 <test_rlwinm_4>:
100020: 54 83 10 3b rlwinm. r3,r4,2,0,29 100020: 54 83 10 3b rlwinm. r3,r4,2,0,29
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_rlwinm_5>: 0000000000100028 <test_rlwinm_5>:
100028: 54 83 01 7a rlwinm r3,r4,0,5,29 100028: 54 83 01 7a rlwinm r3,r4,0,5,29
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_rlwinm_6>: 0000000000100030 <test_rlwinm_6>:
100030: 54 83 00 3e rotlwi r3,r4,0 100030: 54 83 00 3e rotlwi r3,r4,0
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_rlwinm_7>: 0000000000100038 <test_rlwinm_7>:
100038: 54 83 00 20 rlwinm r3,r4,0,0,16 100038: 54 83 00 20 rlwinm r3,r4,0,0,16
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_rlwinm_8>: 0000000000100040 <test_rlwinm_8>:
100040: 54 83 04 3e clrlwi r3,r4,16 100040: 54 83 04 3e clrlwi r3,r4,16
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_rlwinm_9>: 0000000000100048 <test_rlwinm_9>:
100048: 54 83 84 3e rlwinm r3,r4,16,16,31 100048: 54 83 84 3e rlwinm r3,r4,16,16,31
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr

44
src/xenia/cpu/frontend/test/bin/instr_rlwnm.dis
View File

@ -1,45 +1,41 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_rlwnm.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_rlwnm_1>: 0000000000100000 <test_rlwnm_1>:
100000: 5c 83 2a 1e rlwnm r3,r4,r5,8,15 100000: 5c 83 2a 1e rlwnm r3,r4,r5,8,15
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_rlwnm_2>: 0000000000100008 <test_rlwnm_2>:
100008: 5c 83 28 36 rlwnm r3,r4,r5,0,27 100008: 5c 83 28 36 rlwnm r3,r4,r5,0,27
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_rlwnm_3>: 0000000000100010 <test_rlwnm_3>:
100010: 5c 83 28 3a rlwnm r3,r4,r5,0,29 100010: 5c 83 28 3a rlwnm r3,r4,r5,0,29
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_rlwnm_4>: 0000000000100018 <test_rlwnm_4>:
100018: 5c 83 28 3b rlwnm. r3,r4,r5,0,29 100018: 5c 83 28 3b rlwnm. r3,r4,r5,0,29
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_rlwnm_5>: 0000000000100020 <test_rlwnm_5>:
100020: 5c 83 29 7a rlwnm r3,r4,r5,5,29 100020: 5c 83 29 7a rlwnm r3,r4,r5,5,29
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_rlwnm_6>: 0000000000100028 <test_rlwnm_6>:
100028: 5c 83 28 3e rotlw r3,r4,r5 100028: 5c 83 28 3e rotlw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_rlwnm_7>: 0000000000100030 <test_rlwnm_7>:
100030: 5c 83 28 20 rlwnm r3,r4,r5,0,16 100030: 5c 83 28 20 rlwnm r3,r4,r5,0,16
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_rlwnm_8>: 0000000000100038 <test_rlwnm_8>:
100038: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 100038: 5c 83 2c 3e rlwnm r3,r4,r5,16,31
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_rlwnm_9>: 0000000000100040 <test_rlwnm_9>:
100040: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 100040: 5c 83 2c 3e rlwnm r3,r4,r5,16,31
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_rlwnm_10>: 0000000000100048 <test_rlwnm_10>:
100048: 5c 83 28 3e rotlw r3,r4,r5 100048: 5c 83 28 3e rotlw r3,r4,r5
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr

32
src/xenia/cpu/frontend/test/bin/instr_sld.dis
View File

@ -1,33 +1,29 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_sld.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_sld_1>: 0000000000100000 <test_sld_1>:
100000: 7c 83 28 36 sld r3,r4,r5 100000: 7c 83 28 36 sld r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_sld_2>: 0000000000100008 <test_sld_2>:
100008: 7c 83 28 36 sld r3,r4,r5 100008: 7c 83 28 36 sld r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_sld_3>: 0000000000100010 <test_sld_3>:
100010: 7c 83 28 36 sld r3,r4,r5 100010: 7c 83 28 36 sld r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_sld_4>: 0000000000100018 <test_sld_4>:
100018: 7c 83 28 36 sld r3,r4,r5 100018: 7c 83 28 36 sld r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_sld_5>: 0000000000100020 <test_sld_5>:
100020: 7c 83 28 36 sld r3,r4,r5 100020: 7c 83 28 36 sld r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_sld_6>: 0000000000100028 <test_sld_6>:
100028: 7c 83 28 36 sld r3,r4,r5 100028: 7c 83 28 36 sld r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_sld_7>: 0000000000100030 <test_sld_7>:
100030: 7c 83 28 36 sld r3,r4,r5 100030: 7c 83 28 36 sld r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr

40
src/xenia/cpu/frontend/test/bin/instr_slw.dis
View File

@ -1,41 +1,37 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_slw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_slw_1>: 0000000000100000 <test_slw_1>:
100000: 7c 83 28 30 slw r3,r4,r5 100000: 7c 83 28 30 slw r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_slw_2>: 0000000000100008 <test_slw_2>:
100008: 7c 83 28 30 slw r3,r4,r5 100008: 7c 83 28 30 slw r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_slw_3>: 0000000000100010 <test_slw_3>:
100010: 7c 83 28 30 slw r3,r4,r5 100010: 7c 83 28 30 slw r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_slw_4>: 0000000000100018 <test_slw_4>:
100018: 7c 83 28 30 slw r3,r4,r5 100018: 7c 83 28 30 slw r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_slw_5>: 0000000000100020 <test_slw_5>:
100020: 7c 83 28 30 slw r3,r4,r5 100020: 7c 83 28 30 slw r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_slw_6>: 0000000000100028 <test_slw_6>:
100028: 7c 83 28 30 slw r3,r4,r5 100028: 7c 83 28 30 slw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_slw_7>: 0000000000100030 <test_slw_7>:
100030: 7c 83 28 30 slw r3,r4,r5 100030: 7c 83 28 30 slw r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_slw_8>: 0000000000100038 <test_slw_8>:
100038: 7c 83 28 30 slw r3,r4,r5 100038: 7c 83 28 30 slw r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_slw_9>: 0000000000100040 <test_slw_9>:
100040: 7c 83 28 30 slw r3,r4,r5 100040: 7c 83 28 30 slw r3,r4,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr

46
src/xenia/cpu/frontend/test/bin/instr_srad.dis
View File

@ -1,40 +1,36 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_srad.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_srad_1>: 0000000000100000 <test_srad_1>:
100000: 7c 83 2e 34 srad r3,r4,r5 100000: 7c 83 2e 34 srad r3,r4,r5
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_srad_2>: 000000000010000c <test_srad_2>:
10000c: 7c 83 2e 34 srad r3,r4,r5 10000c: 7c 83 2e 34 srad r3,r4,r5
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_srad_3>: 0000000000100018 <test_srad_3>:
100018: 7c 83 2e 34 srad r3,r4,r5 100018: 7c 83 2e 34 srad r3,r4,r5
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_srad_4>: 0000000000100024 <test_srad_4>:
100024: 7c 83 2e 34 srad r3,r4,r5 100024: 7c 83 2e 34 srad r3,r4,r5
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_srad_5>: 0000000000100030 <test_srad_5>:
100030: 7c 83 2e 34 srad r3,r4,r5 100030: 7c 83 2e 34 srad r3,r4,r5
100034: 7c c0 01 14 adde r6,r0,r0 100034: 7c c0 01 14 adde r6,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr
000000000010003c <test_srad_6>: 000000000010003c <test_srad_6>:
10003c: 7c 83 2e 34 srad r3,r4,r5 10003c: 7c 83 2e 34 srad r3,r4,r5
100040: 7c c0 01 14 adde r6,r0,r0 100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_srad_7>: 0000000000100048 <test_srad_7>:
100048: 7c 83 2e 34 srad r3,r4,r5 100048: 7c 83 2e 34 srad r3,r4,r5
10004c: 7c c0 01 14 adde r6,r0,r0 10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr

34
src/xenia/cpu/frontend/test/bin/instr_sradi.dis
View File

@ -1,30 +1,26 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_sradi.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_sradi_1>: 0000000000100000 <test_sradi_1>:
100000: 7c 83 06 74 sradi r3,r4,0 100000: 7c 83 06 74 sradi r3,r4,0
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_sradi_2>: 000000000010000c <test_sradi_2>:
10000c: 7c 83 06 74 sradi r3,r4,0 10000c: 7c 83 06 74 sradi r3,r4,0
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_sradi_3>: 0000000000100018 <test_sradi_3>:
100018: 7c 83 0e 74 sradi r3,r4,1 100018: 7c 83 0e 74 sradi r3,r4,1
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_sradi_4>: 0000000000100024 <test_sradi_4>:
100024: 7c 83 f6 76 sradi r3,r4,62 100024: 7c 83 f6 76 sradi r3,r4,62
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_sradi_5>: 0000000000100030 <test_sradi_5>:
100030: 7c 83 fe 76 sradi r3,r4,63 100030: 7c 83 fe 76 sradi r3,r4,63
100034: 7c c0 01 14 adde r6,r0,r0 100034: 7c c0 01 14 adde r6,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr

58
src/xenia/cpu/frontend/test/bin/instr_sraw.dis
View File

@ -1,50 +1,46 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_sraw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_sraw_1>: 0000000000100000 <test_sraw_1>:
100000: 7c 83 2e 30 sraw r3,r4,r5 100000: 7c 83 2e 30 sraw r3,r4,r5
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_sraw_2>: 000000000010000c <test_sraw_2>:
10000c: 7c 83 2e 30 sraw r3,r4,r5 10000c: 7c 83 2e 30 sraw r3,r4,r5
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_sraw_3>: 0000000000100018 <test_sraw_3>:
100018: 7c 83 2e 30 sraw r3,r4,r5 100018: 7c 83 2e 30 sraw r3,r4,r5
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_sraw_4>: 0000000000100024 <test_sraw_4>:
100024: 7c 83 2e 30 sraw r3,r4,r5 100024: 7c 83 2e 30 sraw r3,r4,r5
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_sraw_5>: 0000000000100030 <test_sraw_5>:
100030: 7c 83 2e 30 sraw r3,r4,r5 100030: 7c 83 2e 30 sraw r3,r4,r5
100034: 7c c0 01 14 adde r6,r0,r0 100034: 7c c0 01 14 adde r6,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr
000000000010003c <test_sraw_6>: 000000000010003c <test_sraw_6>:
10003c: 7c 83 2e 30 sraw r3,r4,r5 10003c: 7c 83 2e 30 sraw r3,r4,r5
100040: 7c c0 01 14 adde r6,r0,r0 100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_sraw_7>: 0000000000100048 <test_sraw_7>:
100048: 7c 83 2e 30 sraw r3,r4,r5 100048: 7c 83 2e 30 sraw r3,r4,r5
10004c: 7c c0 01 14 adde r6,r0,r0 10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr 100050: 4e 80 00 20 blr
0000000000100054 <test_sraw_8>: 0000000000100054 <test_sraw_8>:
100054: 7c 83 2e 30 sraw r3,r4,r5 100054: 7c 83 2e 30 sraw r3,r4,r5
100058: 7c c0 01 14 adde r6,r0,r0 100058: 7c c0 01 14 adde r6,r0,r0
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr
0000000000100060 <test_sraw_9>: 0000000000100060 <test_sraw_9>:
100060: 7c 83 2e 30 sraw r3,r4,r5 100060: 7c 83 2e 30 sraw r3,r4,r5
100064: 7c c0 01 14 adde r6,r0,r0 100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr 100068: 4e 80 00 20 blr

34
src/xenia/cpu/frontend/test/bin/instr_srawi.dis
View File

@ -1,30 +1,26 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_srawi.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_srawi_1>: 0000000000100000 <test_srawi_1>:
100000: 7c 83 06 70 srawi r3,r4,0 100000: 7c 83 06 70 srawi r3,r4,0
100004: 7c c0 01 14 adde r6,r0,r0 100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_srawi_2>: 000000000010000c <test_srawi_2>:
10000c: 7c 83 06 70 srawi r3,r4,0 10000c: 7c 83 06 70 srawi r3,r4,0
100010: 7c c0 01 14 adde r6,r0,r0 100010: 7c c0 01 14 adde r6,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_srawi_3>: 0000000000100018 <test_srawi_3>:
100018: 7c 83 0e 70 srawi r3,r4,1 100018: 7c 83 0e 70 srawi r3,r4,1
10001c: 7c c0 01 14 adde r6,r0,r0 10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_srawi_4>: 0000000000100024 <test_srawi_4>:
100024: 7c 83 f6 70 srawi r3,r4,30 100024: 7c 83 f6 70 srawi r3,r4,30
100028: 7c c0 01 14 adde r6,r0,r0 100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_srawi_5>: 0000000000100030 <test_srawi_5>:
100030: 7c 83 fe 70 srawi r3,r4,31 100030: 7c 83 fe 70 srawi r3,r4,31
100034: 7c c0 01 14 adde r6,r0,r0 100034: 7c c0 01 14 adde r6,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr

32
src/xenia/cpu/frontend/test/bin/instr_srd.dis
View File

@ -1,33 +1,29 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_srd.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_srd_1>: 0000000000100000 <test_srd_1>:
100000: 7c 83 2c 36 srd r3,r4,r5 100000: 7c 83 2c 36 srd r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_srd_2>: 0000000000100008 <test_srd_2>:
100008: 7c 83 2c 36 srd r3,r4,r5 100008: 7c 83 2c 36 srd r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_srd_3>: 0000000000100010 <test_srd_3>:
100010: 7c 83 2c 36 srd r3,r4,r5 100010: 7c 83 2c 36 srd r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_srd_4>: 0000000000100018 <test_srd_4>:
100018: 7c 83 2c 36 srd r3,r4,r5 100018: 7c 83 2c 36 srd r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_srd_5>: 0000000000100020 <test_srd_5>:
100020: 7c 83 2c 36 srd r3,r4,r5 100020: 7c 83 2c 36 srd r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_srd_6>: 0000000000100028 <test_srd_6>:
100028: 7c 83 2c 36 srd r3,r4,r5 100028: 7c 83 2c 36 srd r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_srd_7>: 0000000000100030 <test_srd_7>:
100030: 7c 83 2c 36 srd r3,r4,r5 100030: 7c 83 2c 36 srd r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr

40
src/xenia/cpu/frontend/test/bin/instr_srw.dis
View File

@ -1,41 +1,37 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_srw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_srw_1>: 0000000000100000 <test_srw_1>:
100000: 7c 83 2c 30 srw r3,r4,r5 100000: 7c 83 2c 30 srw r3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_srw_2>: 0000000000100008 <test_srw_2>:
100008: 7c 83 2c 30 srw r3,r4,r5 100008: 7c 83 2c 30 srw r3,r4,r5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_srw_3>: 0000000000100010 <test_srw_3>:
100010: 7c 83 2c 30 srw r3,r4,r5 100010: 7c 83 2c 30 srw r3,r4,r5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_srw_4>: 0000000000100018 <test_srw_4>:
100018: 7c 83 2c 30 srw r3,r4,r5 100018: 7c 83 2c 30 srw r3,r4,r5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_srw_5>: 0000000000100020 <test_srw_5>:
100020: 7c 83 2c 30 srw r3,r4,r5 100020: 7c 83 2c 30 srw r3,r4,r5
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_srw_6>: 0000000000100028 <test_srw_6>:
100028: 7c 83 2c 30 srw r3,r4,r5 100028: 7c 83 2c 30 srw r3,r4,r5
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_srw_7>: 0000000000100030 <test_srw_7>:
100030: 7c 83 2c 30 srw r3,r4,r5 100030: 7c 83 2c 30 srw r3,r4,r5
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_srw_8>: 0000000000100038 <test_srw_8>:
100038: 7c 83 2c 30 srw r3,r4,r5 100038: 7c 83 2c 30 srw r3,r4,r5
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_srw_9>: 0000000000100040 <test_srw_9>:
100040: 7c 83 2c 30 srw r3,r4,r5 100040: 7c 83 2c 30 srw r3,r4,r5
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_stvew.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_stvew.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_stvew_1>: 0000000000100000 <test_stvew_1>:
100000: 7c 60 21 8e stvewx v3,0,r4 100000: 7c 60 21 8e stvewx v3,0,r4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_stvew_2>: 0000000000100008 <test_stvew_2>:
100008: 7c 60 21 8e stvewx v3,0,r4 100008: 7c 60 21 8e stvewx v3,0,r4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_stvew_3>: 0000000000100010 <test_stvew_3>:
100010: 7c 60 21 8e stvewx v3,0,r4 100010: 7c 60 21 8e stvewx v3,0,r4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_stvew_4>: 0000000000100018 <test_stvew_4>:
100018: 7c 60 21 8e stvewx v3,0,r4 100018: 7c 60 21 8e stvewx v3,0,r4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_stvl.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_stvl.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_stvl_1>: 0000000000100000 <test_stvl_1>:
100000: 7c 64 05 0e stvlx v3,r4,r0 100000: 7c 64 05 0e stvlx v3,r4,r0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_stvl_2>: 0000000000100008 <test_stvl_2>:
100008: 7c 64 05 0e stvlx v3,r4,r0 100008: 7c 64 05 0e stvlx v3,r4,r0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_stvr.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_stvr.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_stvr_1>: 0000000000100000 <test_stvr_1>:
100000: 7c 64 2d 4e stvrx v3,r4,r5 100000: 7c 64 2d 4e stvrx v3,r4,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_stvr_2>: 0000000000100008 <test_stvr_2>:
100008: 7c 64 05 4e stvrx v3,r4,r0 100008: 7c 64 05 4e stvrx v3,r4,r0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

24
src/xenia/cpu/frontend/test/bin/instr_subf.dis
View File

@ -1,25 +1,21 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subf.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subf_1>: 0000000000100000 <test_subf_1>:
100000: 7c 6a 58 50 subf r3,r10,r11 100000: 7c 6a 58 50 subf r3,r10,r11
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_subf_2>: 0000000000100008 <test_subf_2>:
100008: 7c 6a 58 50 subf r3,r10,r11 100008: 7c 6a 58 50 subf r3,r10,r11
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_subf_3>: 0000000000100010 <test_subf_3>:
100010: 7c 6a 58 50 subf r3,r10,r11 100010: 7c 6a 58 50 subf r3,r10,r11
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subf_4>: 0000000000100018 <test_subf_4>:
100018: 7c 6a 58 50 subf r3,r10,r11 100018: 7c 6a 58 50 subf r3,r10,r11
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_subf_5>: 0000000000100020 <test_subf_5>:
100020: 7c 6a 58 50 subf r3,r10,r11 100020: 7c 6a 58 50 subf r3,r10,r11
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr

34
src/xenia/cpu/frontend/test/bin/instr_subfc.dis
View File

@ -1,30 +1,26 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subfc.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subfc_1>: 0000000000100000 <test_subfc_1>:
100000: 7c 6a 58 10 subfc r3,r10,r11 100000: 7c 6a 58 10 subfc r3,r10,r11
100004: 7c 80 01 14 adde r4,r0,r0 100004: 7c 80 01 14 adde r4,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_subfc_2>: 000000000010000c <test_subfc_2>:
10000c: 7c 6a 58 10 subfc r3,r10,r11 10000c: 7c 6a 58 10 subfc r3,r10,r11
100010: 7c 80 01 14 adde r4,r0,r0 100010: 7c 80 01 14 adde r4,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subfc_3>: 0000000000100018 <test_subfc_3>:
100018: 7c 6a 58 10 subfc r3,r10,r11 100018: 7c 6a 58 10 subfc r3,r10,r11
10001c: 7c 80 01 14 adde r4,r0,r0 10001c: 7c 80 01 14 adde r4,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_subfc_4>: 0000000000100024 <test_subfc_4>:
100024: 7c 6a 58 10 subfc r3,r10,r11 100024: 7c 6a 58 10 subfc r3,r10,r11
100028: 7c 80 01 14 adde r4,r0,r0 100028: 7c 80 01 14 adde r4,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_subfc_5>: 0000000000100030 <test_subfc_5>:
100030: 7c 6a 58 10 subfc r3,r10,r11 100030: 7c 6a 58 10 subfc r3,r10,r11
100034: 7c 80 01 14 adde r4,r0,r0 100034: 7c 80 01 14 adde r4,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr

34
src/xenia/cpu/frontend/test/bin/instr_subfe.dis
View File

@ -1,30 +1,26 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subfe.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subfe_1>: 0000000000100000 <test_subfe_1>:
100000: 7c 6a 59 10 subfe r3,r10,r11 100000: 7c 6a 59 10 subfe r3,r10,r11
100004: 7c 80 01 14 adde r4,r0,r0 100004: 7c 80 01 14 adde r4,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_subfe_2>: 000000000010000c <test_subfe_2>:
10000c: 7c 6a 59 10 subfe r3,r10,r11 10000c: 7c 6a 59 10 subfe r3,r10,r11
100010: 7c 80 01 14 adde r4,r0,r0 100010: 7c 80 01 14 adde r4,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subfe_3>: 0000000000100018 <test_subfe_3>:
100018: 7c 6a 59 10 subfe r3,r10,r11 100018: 7c 6a 59 10 subfe r3,r10,r11
10001c: 7c 80 01 14 adde r4,r0,r0 10001c: 7c 80 01 14 adde r4,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_subfe_4>: 0000000000100024 <test_subfe_4>:
100024: 7c 6a 59 10 subfe r3,r10,r11 100024: 7c 6a 59 10 subfe r3,r10,r11
100028: 7c 80 01 14 adde r4,r0,r0 100028: 7c 80 01 14 adde r4,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_subfe_5>: 0000000000100030 <test_subfe_5>:
100030: 7c 6a 59 10 subfe r3,r10,r11 100030: 7c 6a 59 10 subfe r3,r10,r11
100034: 7c 80 01 14 adde r4,r0,r0 100034: 7c 80 01 14 adde r4,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr

40
src/xenia/cpu/frontend/test/bin/instr_subfic.dis
View File

@ -1,35 +1,31 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subfic.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subfic_1>: 0000000000100000 <test_subfic_1>:
100000: 20 6a 03 c0 subfic r3,r10,960 100000: 20 6a 03 c0 subfic r3,r10,960
100004: 7c 80 01 14 adde r4,r0,r0 100004: 7c 80 01 14 adde r4,r0,r0
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_subfic_2>: 000000000010000c <test_subfic_2>:
10000c: 20 6a ff 16 subfic r3,r10,-234 10000c: 20 6a ff 16 subfic r3,r10,-234
100010: 7c 80 01 14 adde r4,r0,r0 100010: 7c 80 01 14 adde r4,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subfic_3>: 0000000000100018 <test_subfic_3>:
100018: 20 6a 00 00 subfic r3,r10,0 100018: 20 6a 00 00 subfic r3,r10,0
10001c: 7c 80 01 14 adde r4,r0,r0 10001c: 7c 80 01 14 adde r4,r0,r0
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr
0000000000100024 <test_subfic_4>: 0000000000100024 <test_subfic_4>:
100024: 20 6a 00 00 subfic r3,r10,0 100024: 20 6a 00 00 subfic r3,r10,0
100028: 7c 80 01 14 adde r4,r0,r0 100028: 7c 80 01 14 adde r4,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_subfic_5>: 0000000000100030 <test_subfic_5>:
100030: 20 6a 00 01 subfic r3,r10,1 100030: 20 6a 00 01 subfic r3,r10,1
100034: 7c 80 01 14 adde r4,r0,r0 100034: 7c 80 01 14 adde r4,r0,r0
100038: 4e 80 00 20 blr 100038: 4e 80 00 20 blr
000000000010003c <test_subfic_6>: 000000000010003c <test_subfic_6>:
10003c: 20 6a ff ff subfic r3,r10,-1 10003c: 20 6a ff ff subfic r3,r10,-1
100040: 7c 80 01 14 adde r4,r0,r0 100040: 7c 80 01 14 adde r4,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr

92
src/xenia/cpu/frontend/test/bin/instr_subfme.dis
View File

@ -1,65 +1,61 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subfme.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subfme_one_ca_1>: 0000000000100000 <test_subfme_one_ca_1>:
100000: 7c 63 1a 78 xor r3,r3,r3 100000: 7c 63 1a 78 xor r3,r3,r3
100004: 7c 63 18 f8 not r3,r3 100004: 7c 63 18 f8 not r3,r3
100008: 30 63 00 01 addic r3,r3,1 100008: 30 63 00 01 addic r3,r3,1
10000c: 7c 6a 01 d0 subfme r3,r10 10000c: 7c 6a 01 d0 subfme r3,r10
100010: 7c 80 01 14 adde r4,r0,r0 100010: 7c 80 01 14 adde r4,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subfme_one_ca_2>: 0000000000100018 <test_subfme_one_ca_2>:
100018: 7c 63 1a 78 xor r3,r3,r3 100018: 7c 63 1a 78 xor r3,r3,r3
10001c: 7c 63 18 f8 not r3,r3 10001c: 7c 63 18 f8 not r3,r3
100020: 30 63 00 01 addic r3,r3,1 100020: 30 63 00 01 addic r3,r3,1
100024: 7c 6a 01 d0 subfme r3,r10 100024: 7c 6a 01 d0 subfme r3,r10
100028: 7c 80 01 14 adde r4,r0,r0 100028: 7c 80 01 14 adde r4,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_subfme_one_ca_3>: 0000000000100030 <test_subfme_one_ca_3>:
100030: 7c 63 1a 78 xor r3,r3,r3 100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3 100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1 100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 6a 01 d0 subfme r3,r10 10003c: 7c 6a 01 d0 subfme r3,r10
100040: 7c 80 01 14 adde r4,r0,r0 100040: 7c 80 01 14 adde r4,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_subfme_one_ca_4>: 0000000000100048 <test_subfme_one_ca_4>:
100048: 7c 63 1a 78 xor r3,r3,r3 100048: 7c 63 1a 78 xor r3,r3,r3
10004c: 7c 63 18 f8 not r3,r3 10004c: 7c 63 18 f8 not r3,r3
100050: 30 63 00 01 addic r3,r3,1 100050: 30 63 00 01 addic r3,r3,1
100054: 7c 6a 01 d0 subfme r3,r10 100054: 7c 6a 01 d0 subfme r3,r10
100058: 7c 80 01 14 adde r4,r0,r0 100058: 7c 80 01 14 adde r4,r0,r0
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr
0000000000100060 <test_subfme_zero_ca_1>: 0000000000100060 <test_subfme_zero_ca_1>:
100060: 7c 63 1a 78 xor r3,r3,r3 100060: 7c 63 1a 78 xor r3,r3,r3
100064: 30 63 00 01 addic r3,r3,1 100064: 30 63 00 01 addic r3,r3,1
100068: 7c 6a 01 d0 subfme r3,r10 100068: 7c 6a 01 d0 subfme r3,r10
10006c: 7c 80 01 14 adde r4,r0,r0 10006c: 7c 80 01 14 adde r4,r0,r0
100070: 4e 80 00 20 blr 100070: 4e 80 00 20 blr
0000000000100074 <test_subfme_zero_ca_2>: 0000000000100074 <test_subfme_zero_ca_2>:
100074: 7c 63 1a 78 xor r3,r3,r3 100074: 7c 63 1a 78 xor r3,r3,r3
100078: 30 63 00 01 addic r3,r3,1 100078: 30 63 00 01 addic r3,r3,1
10007c: 7c 6a 01 d0 subfme r3,r10 10007c: 7c 6a 01 d0 subfme r3,r10
100080: 7c 80 01 14 adde r4,r0,r0 100080: 7c 80 01 14 adde r4,r0,r0
100084: 4e 80 00 20 blr 100084: 4e 80 00 20 blr
0000000000100088 <test_subfme_zero_ca_3>: 0000000000100088 <test_subfme_zero_ca_3>:
100088: 7c 63 1a 78 xor r3,r3,r3 100088: 7c 63 1a 78 xor r3,r3,r3
10008c: 30 63 00 01 addic r3,r3,1 10008c: 30 63 00 01 addic r3,r3,1
100090: 7c 6a 01 d0 subfme r3,r10 100090: 7c 6a 01 d0 subfme r3,r10
100094: 7c 80 01 14 adde r4,r0,r0 100094: 7c 80 01 14 adde r4,r0,r0
100098: 4e 80 00 20 blr 100098: 4e 80 00 20 blr
000000000010009c <test_subfme_zero_ca_4>: 000000000010009c <test_subfme_zero_ca_4>:
10009c: 7c 63 1a 78 xor r3,r3,r3 10009c: 7c 63 1a 78 xor r3,r3,r3
1000a0: 30 63 00 01 addic r3,r3,1 1000a0: 30 63 00 01 addic r3,r3,1
1000a4: 7c 6a 01 d0 subfme r3,r10 1000a4: 7c 6a 01 d0 subfme r3,r10
1000a8: 7c 80 01 14 adde r4,r0,r0 1000a8: 7c 80 01 14 adde r4,r0,r0
1000ac: 4e 80 00 20 blr 1000ac: 4e 80 00 20 blr

92
src/xenia/cpu/frontend/test/bin/instr_subfze.dis
View File

@ -1,65 +1,61 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_subfze.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_subfze_one_ca_1>: 0000000000100000 <test_subfze_one_ca_1>:
100000: 7c 63 1a 78 xor r3,r3,r3 100000: 7c 63 1a 78 xor r3,r3,r3
100004: 7c 63 18 f8 not r3,r3 100004: 7c 63 18 f8 not r3,r3
100008: 30 63 00 01 addic r3,r3,1 100008: 30 63 00 01 addic r3,r3,1
10000c: 7c 6a 01 90 subfze r3,r10 10000c: 7c 6a 01 90 subfze r3,r10
100010: 7c 80 01 14 adde r4,r0,r0 100010: 7c 80 01 14 adde r4,r0,r0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_subfze_one_ca_2>: 0000000000100018 <test_subfze_one_ca_2>:
100018: 7c 63 1a 78 xor r3,r3,r3 100018: 7c 63 1a 78 xor r3,r3,r3
10001c: 7c 63 18 f8 not r3,r3 10001c: 7c 63 18 f8 not r3,r3
100020: 30 63 00 01 addic r3,r3,1 100020: 30 63 00 01 addic r3,r3,1
100024: 7c 6a 01 90 subfze r3,r10 100024: 7c 6a 01 90 subfze r3,r10
100028: 7c 80 01 14 adde r4,r0,r0 100028: 7c 80 01 14 adde r4,r0,r0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_subfze_one_ca_3>: 0000000000100030 <test_subfze_one_ca_3>:
100030: 7c 63 1a 78 xor r3,r3,r3 100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3 100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1 100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 6a 01 90 subfze r3,r10 10003c: 7c 6a 01 90 subfze r3,r10
100040: 7c 80 01 14 adde r4,r0,r0 100040: 7c 80 01 14 adde r4,r0,r0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_subfze_one_ca_4>: 0000000000100048 <test_subfze_one_ca_4>:
100048: 7c 63 1a 78 xor r3,r3,r3 100048: 7c 63 1a 78 xor r3,r3,r3
10004c: 7c 63 18 f8 not r3,r3 10004c: 7c 63 18 f8 not r3,r3
100050: 30 63 00 01 addic r3,r3,1 100050: 30 63 00 01 addic r3,r3,1
100054: 7c 6a 01 90 subfze r3,r10 100054: 7c 6a 01 90 subfze r3,r10
100058: 7c 80 01 14 adde r4,r0,r0 100058: 7c 80 01 14 adde r4,r0,r0
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr
0000000000100060 <test_subfze_zero_ca_1>: 0000000000100060 <test_subfze_zero_ca_1>:
100060: 7c 63 1a 78 xor r3,r3,r3 100060: 7c 63 1a 78 xor r3,r3,r3
100064: 30 63 00 01 addic r3,r3,1 100064: 30 63 00 01 addic r3,r3,1
100068: 7c 6a 01 90 subfze r3,r10 100068: 7c 6a 01 90 subfze r3,r10
10006c: 7c 80 01 14 adde r4,r0,r0 10006c: 7c 80 01 14 adde r4,r0,r0
100070: 4e 80 00 20 blr 100070: 4e 80 00 20 blr
0000000000100074 <test_subfze_zero_ca_2>: 0000000000100074 <test_subfze_zero_ca_2>:
100074: 7c 63 1a 78 xor r3,r3,r3 100074: 7c 63 1a 78 xor r3,r3,r3
100078: 30 63 00 01 addic r3,r3,1 100078: 30 63 00 01 addic r3,r3,1
10007c: 7c 6a 01 90 subfze r3,r10 10007c: 7c 6a 01 90 subfze r3,r10
100080: 7c 80 01 14 adde r4,r0,r0 100080: 7c 80 01 14 adde r4,r0,r0
100084: 4e 80 00 20 blr 100084: 4e 80 00 20 blr
0000000000100088 <test_subfze_zero_ca_3>: 0000000000100088 <test_subfze_zero_ca_3>:
100088: 7c 63 1a 78 xor r3,r3,r3 100088: 7c 63 1a 78 xor r3,r3,r3
10008c: 30 63 00 01 addic r3,r3,1 10008c: 30 63 00 01 addic r3,r3,1
100090: 7c 6a 01 90 subfze r3,r10 100090: 7c 6a 01 90 subfze r3,r10
100094: 7c 80 01 14 adde r4,r0,r0 100094: 7c 80 01 14 adde r4,r0,r0
100098: 4e 80 00 20 blr 100098: 4e 80 00 20 blr
000000000010009c <test_subfze_zero_ca_4>: 000000000010009c <test_subfze_zero_ca_4>:
10009c: 7c 63 1a 78 xor r3,r3,r3 10009c: 7c 63 1a 78 xor r3,r3,r3
1000a0: 30 63 00 01 addic r3,r3,1 1000a0: 30 63 00 01 addic r3,r3,1
1000a4: 7c 6a 01 90 subfze r3,r10 1000a4: 7c 6a 01 90 subfze r3,r10
1000a8: 7c 80 01 14 adde r4,r0,r0 1000a8: 7c 80 01 14 adde r4,r0,r0
1000ac: 4e 80 00 20 blr 1000ac: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vaddshs.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vaddshs.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vaddshs_1>: 0000000000100000 <test_vaddshs_1>:
100000: 10 63 23 40 vaddshs v3,v3,v4 100000: 10 63 23 40 vaddshs v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vadduhm.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vadduhm.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vadduhm_1>: 0000000000100000 <test_vadduhm_1>:
100000: 10 63 20 40 vadduhm v3,v3,v4 100000: 10 63 20 40 vadduhm v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vcfsx.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vcfsx.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vcfsx_1>: 0000000000100000 <test_vcfsx_1>:
100000: 10 60 1b 4a vcfsx v3,v3,0 100000: 10 60 1b 4a vcfsx v3,v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vcfsx_2>: 0000000000100008 <test_vcfsx_2>:
100008: 10 61 1b 4a vcfsx v3,v3,1 100008: 10 61 1b 4a vcfsx v3,v3,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vcfsx_3>: 0000000000100010 <test_vcfsx_3>:
100010: 10 6a 1b 4a vcfsx v3,v3,10 100010: 10 6a 1b 4a vcfsx v3,v3,10
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

22
src/xenia/cpu/frontend/test/bin/instr_vcmpxxfp.dis
View File

@ -1,20 +1,16 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vcmpxxfp.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vcmpxxfp_1>: 0000000000100000 <test_vcmpxxfp_1>:
100000: 10 64 2c c6 .long 0x10642cc6 100000: 10 64 2c c6 .long 0x10642cc6
100004: 7c 70 20 26 mfocrf r3,2 100004: 7c 70 20 26 mfocrf r3,2
100008: 4e 80 00 20 blr 100008: 4e 80 00 20 blr
000000000010000c <test_vcmpxxfp_2>: 000000000010000c <test_vcmpxxfp_2>:
10000c: 10 64 2c c6 .long 0x10642cc6 10000c: 10 64 2c c6 .long 0x10642cc6
100010: 7c 70 20 26 mfocrf r3,2 100010: 7c 70 20 26 mfocrf r3,2
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vcmpxxfp_3>: 0000000000100018 <test_vcmpxxfp_3>:
100018: 10 64 2c c6 .long 0x10642cc6 100018: 10 64 2c c6 .long 0x10642cc6
10001c: 7c 70 20 26 mfocrf r3,2 10001c: 7c 70 20 26 mfocrf r3,2
100020: 4e 80 00 20 blr 100020: 4e 80 00 20 blr

24
src/xenia/cpu/frontend/test/bin/instr_vctsxs.dis
View File

@ -1,25 +1,21 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vctsxs.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vctsxs_1>: 0000000000100000 <test_vctsxs_1>:
100000: 10 60 1b ca vctsxs v3,v3,0 100000: 10 60 1b ca vctsxs v3,v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vctsxs_2>: 0000000000100008 <test_vctsxs_2>:
100008: 10 61 1b ca vctsxs v3,v3,1 100008: 10 61 1b ca vctsxs v3,v3,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vctsxs_3>: 0000000000100010 <test_vctsxs_3>:
100010: 10 62 1b ca vctsxs v3,v3,2 100010: 10 62 1b ca vctsxs v3,v3,2
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vctsxs_4>: 0000000000100018 <test_vctsxs_4>:
100018: 10 60 1b ca vctsxs v3,v3,0 100018: 10 60 1b ca vctsxs v3,v3,0
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vctsxs_5>: 0000000000100020 <test_vctsxs_5>:
100020: 10 61 1b ca vctsxs v3,v3,1 100020: 10 61 1b ca vctsxs v3,v3,1
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrghb.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrghb.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrghb_1>: 0000000000100000 <test_vmrghb_1>:
100000: 10 a3 20 0c vmrghb v5,v3,v4 100000: 10 a3 20 0c vmrghb v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrghh.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrghh.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrghh_1>: 0000000000100000 <test_vmrghh_1>:
100000: 10 a3 20 4c vmrghh v5,v3,v4 100000: 10 a3 20 4c vmrghh v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrghw.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrghw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrghw_1>: 0000000000100000 <test_vmrghw_1>:
100000: 10 a3 20 8c vmrghw v5,v3,v4 100000: 10 a3 20 8c vmrghw v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrglb.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrglb.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrglb_1>: 0000000000100000 <test_vmrglb_1>:
100000: 10 a3 21 0c vmrglb v5,v3,v4 100000: 10 a3 21 0c vmrglb v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrglh.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrglh.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrglh_1>: 0000000000100000 <test_vmrglh_1>:
100000: 10 a3 21 4c vmrglh v5,v3,v4 100000: 10 a3 21 4c vmrglh v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vmrglw.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vmrglw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vmrglw_1>: 0000000000100000 <test_vmrglw_1>:
100000: 10 a3 21 8c vmrglw v5,v3,v4 100000: 10 a3 21 8c vmrglw v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_vperm.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vperm.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vperm_1>: 0000000000100000 <test_vperm_1>:
100000: 10 c3 21 6b vperm v6,v3,v4,v5 100000: 10 c3 21 6b vperm v6,v3,v4,v5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vperm_2>: 0000000000100008 <test_vperm_2>:
100008: 10 c3 21 6b vperm v6,v3,v4,v5 100008: 10 c3 21 6b vperm v6,v3,v4,v5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vperm_3>: 0000000000100010 <test_vperm_3>:
100010: 10 c3 21 6b vperm v6,v3,v4,v5 100010: 10 c3 21 6b vperm v6,v3,v4,v5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vperm_4>: 0000000000100018 <test_vperm_4>:
100018: 10 c3 21 6b vperm v6,v3,v4,v5 100018: 10 c3 21 6b vperm v6,v3,v4,v5
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_vpermwi128.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vpermwi128.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vpermwi128_1>: 0000000000100000 <test_vpermwi128_1>:
100000: 18 9b 1a 10 vpermwi128 v4,v3,27 100000: 18 9b 1a 10 vpermwi128 v4,v3,27
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vpermwi128_2>: 0000000000100008 <test_vpermwi128_2>:
100008: 18 84 1b d0 vpermwi128 v4,v3,228 100008: 18 84 1b d0 vpermwi128 v4,v3,228
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vpermwi128_3>: 0000000000100010 <test_vpermwi128_3>:
100010: 18 80 1a 10 vpermwi128 v4,v3,0 100010: 18 80 1a 10 vpermwi128 v4,v3,0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vpermwi128_4>: 0000000000100018 <test_vpermwi128_4>:
100018: 18 9f 1b d0 vpermwi128 v4,v3,255 100018: 18 9f 1b d0 vpermwi128 v4,v3,255
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

96
src/xenia/cpu/frontend/test/bin/instr_vpkd3d128.dis
View File

@ -1,97 +1,93 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vpkd3d128.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vpkd3d128_d3dcolor_invalid_0>: 0000000000100000 <test_vpkd3d128_d3dcolor_invalid_0>:
100000: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0 100000: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vpkd3d128_d3dcolor_invalid_1>: 0000000000100008 <test_vpkd3d128_d3dcolor_invalid_1>:
100008: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0 100008: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vpkd3d128_d3dcolor_1_0>: 0000000000100010 <test_vpkd3d128_d3dcolor_1_0>:
100010: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0 100010: 18 81 1e 10 vpkd3d128 v4,v3,0,0,0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vpkd3d128_d3dcolor_1_1>: 0000000000100018 <test_vpkd3d128_d3dcolor_1_1>:
100018: 18 81 1e 50 vpkd3d128 v4,v3,0,0,0 100018: 18 81 1e 50 vpkd3d128 v4,v3,0,0,0
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vpkd3d128_d3dcolor_1_2>: 0000000000100020 <test_vpkd3d128_d3dcolor_1_2>:
100020: 18 81 1e 90 vpkd3d128 v4,v3,0,0,2 100020: 18 81 1e 90 vpkd3d128 v4,v3,0,0,2
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_vpkd3d128_d3dcolor_1_3>: 0000000000100028 <test_vpkd3d128_d3dcolor_1_3>:
100028: 18 81 1e d0 vpkd3d128 v4,v3,0,0,2 100028: 18 81 1e d0 vpkd3d128 v4,v3,0,0,2
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_vpkd3d128_d3dcolor_2_0>: 0000000000100030 <test_vpkd3d128_d3dcolor_2_0>:
100030: 18 82 1e 10 vpkd3d128 v4,v3,0,2,0 100030: 18 82 1e 10 vpkd3d128 v4,v3,0,2,0
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_vpkd3d128_d3dcolor_2_1>: 0000000000100038 <test_vpkd3d128_d3dcolor_2_1>:
100038: 18 82 1e 50 vpkd3d128 v4,v3,0,2,0 100038: 18 82 1e 50 vpkd3d128 v4,v3,0,2,0
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_vpkd3d128_d3dcolor_2_2>: 0000000000100040 <test_vpkd3d128_d3dcolor_2_2>:
100040: 18 82 1e 90 vpkd3d128 v4,v3,0,2,2 100040: 18 82 1e 90 vpkd3d128 v4,v3,0,2,2
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr
0000000000100048 <test_vpkd3d128_d3dcolor_2_3>: 0000000000100048 <test_vpkd3d128_d3dcolor_2_3>:
100048: 18 82 1e d0 vpkd3d128 v4,v3,0,2,2 100048: 18 82 1e d0 vpkd3d128 v4,v3,0,2,2
10004c: 4e 80 00 20 blr 10004c: 4e 80 00 20 blr
0000000000100050 <test_vpkd3d128_d3dcolor_3_0>: 0000000000100050 <test_vpkd3d128_d3dcolor_3_0>:
100050: 18 83 1e 10 vpkd3d128 v4,v3,0,2,0 100050: 18 83 1e 10 vpkd3d128 v4,v3,0,2,0
100054: 4e 80 00 20 blr 100054: 4e 80 00 20 blr
0000000000100058 <test_vpkd3d128_d3dcolor_3_1>: 0000000000100058 <test_vpkd3d128_d3dcolor_3_1>:
100058: 18 83 1e 50 vpkd3d128 v4,v3,0,2,0 100058: 18 83 1e 50 vpkd3d128 v4,v3,0,2,0
10005c: 4e 80 00 20 blr 10005c: 4e 80 00 20 blr
0000000000100060 <test_vpkd3d128_d3dcolor_3_2>: 0000000000100060 <test_vpkd3d128_d3dcolor_3_2>:
100060: 18 83 1e 90 vpkd3d128 v4,v3,0,2,2 100060: 18 83 1e 90 vpkd3d128 v4,v3,0,2,2
100064: 4e 80 00 20 blr 100064: 4e 80 00 20 blr
0000000000100068 <test_vpkd3d128_d3dcolor_3_3>: 0000000000100068 <test_vpkd3d128_d3dcolor_3_3>:
100068: 18 83 1e d0 vpkd3d128 v4,v3,0,2,2 100068: 18 83 1e d0 vpkd3d128 v4,v3,0,2,2
10006c: 4e 80 00 20 blr 10006c: 4e 80 00 20 blr
0000000000100070 <test_vpkd3d128_short2_invalid_0>: 0000000000100070 <test_vpkd3d128_short2_invalid_0>:
100070: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0 100070: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0
100074: 4e 80 00 20 blr 100074: 4e 80 00 20 blr
0000000000100078 <test_vpkd3d128_short2_invalid_1>: 0000000000100078 <test_vpkd3d128_short2_invalid_1>:
100078: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0 100078: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0
10007c: 4e 80 00 20 blr 10007c: 4e 80 00 20 blr
0000000000100080 <test_vpkd3d128_short2_0>: 0000000000100080 <test_vpkd3d128_short2_0>:
100080: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0 100080: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0
100084: 4e 80 00 20 blr 100084: 4e 80 00 20 blr
0000000000100088 <test_vpkd3d128_short2_1>: 0000000000100088 <test_vpkd3d128_short2_1>:
100088: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0 100088: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0
10008c: 4e 80 00 20 blr 10008c: 4e 80 00 20 blr
0000000000100090 <test_vpkd3d128_short2_2>: 0000000000100090 <test_vpkd3d128_short2_2>:
100090: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0 100090: 18 85 1e 10 vpkd3d128 v4,v3,1,0,0
100094: 4e 80 00 20 blr 100094: 4e 80 00 20 blr
0000000000100098 <test_vpkd3d128_float16_2_invalid_0>: 0000000000100098 <test_vpkd3d128_float16_2_invalid_0>:
100098: 18 8d 1e 10 vpkd3d128 v4,v3,3,0,0 100098: 18 8d 1e 10 vpkd3d128 v4,v3,3,0,0
10009c: 4e 80 00 20 blr 10009c: 4e 80 00 20 blr
00000000001000a0 <test_vpkd3d128_float16_2_0>: 00000000001000a0 <test_vpkd3d128_float16_2_0>:
1000a0: 18 8d 1e 10 vpkd3d128 v4,v3,3,0,0 1000a0: 18 8d 1e 10 vpkd3d128 v4,v3,3,0,0
1000a4: 4e 80 00 20 blr 1000a4: 4e 80 00 20 blr
00000000001000a8 <test_vpkd3d128_float16_4_invalid_0>: 00000000001000a8 <test_vpkd3d128_float16_4_invalid_0>:
1000a8: 18 96 1e 10 vpkd3d128 v4,v3,1,2,0 1000a8: 18 96 1e 10 vpkd3d128 v4,v3,1,2,0
1000ac: 4e 80 00 20 blr 1000ac: 4e 80 00 20 blr
00000000001000b0 <test_vpkd3d128_float16_4_0>: 00000000001000b0 <test_vpkd3d128_float16_4_0>:
1000b0: 18 96 1e 10 vpkd3d128 v4,v3,1,2,0 1000b0: 18 96 1e 10 vpkd3d128 v4,v3,1,2,0
1000b4: 4e 80 00 20 blr 1000b4: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_vpkshss.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vpkshss.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vpkshss_0>: 0000000000100000 <test_vpkshss_0>:
100000: 10 a3 21 8e vpkshss v5,v3,v4 100000: 10 a3 21 8e vpkshss v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vpkshss_1>: 0000000000100008 <test_vpkshss_1>:
100008: 10 a3 21 8e vpkshss v5,v3,v4 100008: 10 a3 21 8e vpkshss v5,v3,v4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_vpkswss.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vpkswss.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vpkswss_0>: 0000000000100000 <test_vpkswss_0>:
100000: 10 a3 21 ce vpkswss v5,v3,v4 100000: 10 a3 21 ce vpkswss v5,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vpkswss_1>: 0000000000100008 <test_vpkswss_1>:
100008: 10 a3 21 ce vpkswss v5,v3,v4 100008: 10 a3 21 ce vpkswss v5,v3,v4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_vrfin.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vrfin.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vrfin_1>: 0000000000100000 <test_vrfin_1>:
100000: 10 60 1a 0a vrfin v3,v3 100000: 10 60 1a 0a vrfin v3,v3
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vrfin_2>: 0000000000100008 <test_vrfin_2>:
100008: 10 60 1a 0a vrfin v3,v3 100008: 10 60 1a 0a vrfin v3,v3
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

40
src/xenia/cpu/frontend/test/bin/instr_vrlimi128.dis
View File

@ -1,41 +1,37 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vrlimi128.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vrlimi128_1>: 0000000000100000 <test_vrlimi128_1>:
100000: 18 80 1f 10 vrlimi128 v4,v3,0,0 100000: 18 80 1f 10 vrlimi128 v4,v3,0,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vrlimi128_2>: 0000000000100008 <test_vrlimi128_2>:
100008: 18 8f 1f 10 vrlimi128 v4,v3,15,0 100008: 18 8f 1f 10 vrlimi128 v4,v3,15,0
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vrlimi128_3>: 0000000000100010 <test_vrlimi128_3>:
100010: 18 8f 1f 50 vrlimi128 v4,v3,15,0 100010: 18 8f 1f 50 vrlimi128 v4,v3,15,0
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vrlimi128_4>: 0000000000100018 <test_vrlimi128_4>:
100018: 18 8f 1f 90 vrlimi128 v4,v3,15,2 100018: 18 8f 1f 90 vrlimi128 v4,v3,15,2
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vrlimi128_5>: 0000000000100020 <test_vrlimi128_5>:
100020: 18 8f 1f d0 vrlimi128 v4,v3,15,2 100020: 18 8f 1f d0 vrlimi128 v4,v3,15,2
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_vrlimi128_6>: 0000000000100028 <test_vrlimi128_6>:
100028: 18 88 1f 10 vrlimi128 v4,v3,8,0 100028: 18 88 1f 10 vrlimi128 v4,v3,8,0
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr
0000000000100030 <test_vrlimi128_7>: 0000000000100030 <test_vrlimi128_7>:
100030: 18 84 1f 10 vrlimi128 v4,v3,4,0 100030: 18 84 1f 10 vrlimi128 v4,v3,4,0
100034: 4e 80 00 20 blr 100034: 4e 80 00 20 blr
0000000000100038 <test_vrlimi128_8>: 0000000000100038 <test_vrlimi128_8>:
100038: 18 82 1f 10 vrlimi128 v4,v3,2,0 100038: 18 82 1f 10 vrlimi128 v4,v3,2,0
10003c: 4e 80 00 20 blr 10003c: 4e 80 00 20 blr
0000000000100040 <test_vrlimi128_9>: 0000000000100040 <test_vrlimi128_9>:
100040: 18 81 1f 10 vrlimi128 v4,v3,1,0 100040: 18 81 1f 10 vrlimi128 v4,v3,1,0
100044: 4e 80 00 20 blr 100044: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vsel.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vsel.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vsel_1>: 0000000000100000 <test_vsel_1>:
100000: 10 a3 21 6a vsel v5,v3,v4,v5 100000: 10 a3 21 6a vsel v5,v3,v4,v5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vsel_2>: 0000000000100008 <test_vsel_2>:
100008: 10 a3 21 6a vsel v5,v3,v4,v5 100008: 10 a3 21 6a vsel v5,v3,v4,v5
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vsel_3>: 0000000000100010 <test_vsel_3>:
100010: 10 a3 21 6a vsel v5,v3,v4,v5 100010: 10 a3 21 6a vsel v5,v3,v4,v5
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

24
src/xenia/cpu/frontend/test/bin/instr_vslb.dis
View File

@ -1,25 +1,21 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vslb.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vslb_1>: 0000000000100000 <test_vslb_1>:
100000: 10 63 21 04 vslb v3,v3,v4 100000: 10 63 21 04 vslb v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vslb_2>: 0000000000100008 <test_vslb_2>:
100008: 10 63 21 04 vslb v3,v3,v4 100008: 10 63 21 04 vslb v3,v3,v4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vslb_3>: 0000000000100010 <test_vslb_3>:
100010: 10 63 21 04 vslb v3,v3,v4 100010: 10 63 21 04 vslb v3,v3,v4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vslb_4>: 0000000000100018 <test_vslb_4>:
100018: 10 63 21 04 vslb v3,v3,v4 100018: 10 63 21 04 vslb v3,v3,v4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vslb_5>: 0000000000100020 <test_vslb_5>:
100020: 10 63 21 04 vslb v3,v3,v4 100020: 10 63 21 04 vslb v3,v3,v4
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vsldoi.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vsldoi.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vsldoi_1>: 0000000000100000 <test_vsldoi_1>:
100000: 10 a3 20 2c vsldoi v5,v3,v4,0 100000: 10 a3 20 2c vsldoi v5,v3,v4,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vsldoi_2>: 0000000000100008 <test_vsldoi_2>:
100008: 10 a3 20 6c vsldoi v5,v3,v4,1 100008: 10 a3 20 6c vsldoi v5,v3,v4,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vsldoi_3>: 0000000000100010 <test_vsldoi_3>:
100010: 10 a3 23 ec vsldoi v5,v3,v4,15 100010: 10 a3 23 ec vsldoi v5,v3,v4,15
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_vslh.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vslh.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vslh_1>: 0000000000100000 <test_vslh_1>:
100000: 10 63 21 44 vslh v3,v3,v4 100000: 10 63 21 44 vslh v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vslh_2>: 0000000000100008 <test_vslh_2>:
100008: 10 63 21 44 vslh v3,v3,v4 100008: 10 63 21 44 vslh v3,v3,v4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vslh_3>: 0000000000100010 <test_vslh_3>:
100010: 10 63 21 44 vslh v3,v3,v4 100010: 10 63 21 44 vslh v3,v3,v4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vslh_4>: 0000000000100018 <test_vslh_4>:
100018: 10 63 21 44 vslh v3,v3,v4 100018: 10 63 21 44 vslh v3,v3,v4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vslh_5>: 0000000000100020 <test_vslh_5>:
100020: 10 63 21 44 vslh v3,v3,v4 100020: 10 63 21 44 vslh v3,v3,v4
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_vslh_6>: 0000000000100028 <test_vslh_6>:
100028: 10 63 21 44 vslh v3,v3,v4 100028: 10 63 21 44 vslh v3,v3,v4
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_vslw.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vslw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vslw_1>: 0000000000100000 <test_vslw_1>:
100000: 10 63 21 84 vslw v3,v3,v4 100000: 10 63 21 84 vslw v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vslw_2>: 0000000000100008 <test_vslw_2>:
100008: 10 63 21 84 vslw v3,v3,v4 100008: 10 63 21 84 vslw v3,v3,v4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vslw_3>: 0000000000100010 <test_vslw_3>:
100010: 10 63 21 84 vslw v3,v3,v4 100010: 10 63 21 84 vslw v3,v3,v4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vslw_4>: 0000000000100018 <test_vslw_4>:
100018: 10 63 21 84 vslw v3,v3,v4 100018: 10 63 21 84 vslw v3,v3,v4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vslw_5>: 0000000000100020 <test_vslw_5>:
100020: 10 63 21 84 vslw v3,v3,v4 100020: 10 63 21 84 vslw v3,v3,v4
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_vslw_6>: 0000000000100028 <test_vslw_6>:
100028: 10 63 21 84 vslw v3,v3,v4 100028: 10 63 21 84 vslw v3,v3,v4
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vspltb.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vspltb.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vspltb_1>: 0000000000100000 <test_vspltb_1>:
100000: 10 60 22 0c vspltb v3,v4,0 100000: 10 60 22 0c vspltb v3,v4,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vspltb_2>: 0000000000100008 <test_vspltb_2>:
100008: 10 61 22 0c vspltb v3,v4,1 100008: 10 61 22 0c vspltb v3,v4,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vspltb_3>: 0000000000100010 <test_vspltb_3>:
100010: 10 6f 22 0c vspltb v3,v4,15 100010: 10 6f 22 0c vspltb v3,v4,15
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vsplth.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vsplth.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vsplth_1>: 0000000000100000 <test_vsplth_1>:
100000: 10 60 22 4c vsplth v3,v4,0 100000: 10 60 22 4c vsplth v3,v4,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vsplth_2>: 0000000000100008 <test_vsplth_2>:
100008: 10 61 22 4c vsplth v3,v4,1 100008: 10 61 22 4c vsplth v3,v4,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vsplth_3>: 0000000000100010 <test_vsplth_3>:
100010: 10 67 22 4c vsplth v3,v4,7 100010: 10 67 22 4c vsplth v3,v4,7
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_vspltisb.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vspltisb.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vspltisb_1>: 0000000000100000 <test_vspltisb_1>:
100000: 10 60 03 0c vspltisb v3,0 100000: 10 60 03 0c vspltisb v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vspltisb_2>: 0000000000100008 <test_vspltisb_2>:
100008: 10 61 03 0c vspltisb v3,1 100008: 10 61 03 0c vspltisb v3,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vspltisb_3>: 0000000000100010 <test_vspltisb_3>:
100010: 10 7f 03 0c vspltisb v3,-1 100010: 10 7f 03 0c vspltisb v3,-1
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vspltisb_4>: 0000000000100018 <test_vspltisb_4>:
100018: 10 7e 03 0c vspltisb v3,-2 100018: 10 7e 03 0c vspltisb v3,-2
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_vspltish.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vspltish.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vspltish_1>: 0000000000100000 <test_vspltish_1>:
100000: 10 60 03 4c vspltish v3,0 100000: 10 60 03 4c vspltish v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vspltish_2>: 0000000000100008 <test_vspltish_2>:
100008: 10 61 03 4c vspltish v3,1 100008: 10 61 03 4c vspltish v3,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vspltish_3>: 0000000000100010 <test_vspltish_3>:
100010: 10 7f 03 4c vspltish v3,-1 100010: 10 7f 03 4c vspltish v3,-1
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vspltish_4>: 0000000000100018 <test_vspltish_4>:
100018: 10 7e 03 4c vspltish v3,-2 100018: 10 7e 03 4c vspltish v3,-2
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

20
src/xenia/cpu/frontend/test/bin/instr_vspltisw.dis
View File

@ -1,21 +1,17 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vspltisw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vspltisw_1>: 0000000000100000 <test_vspltisw_1>:
100000: 10 60 03 8c vspltisw v3,0 100000: 10 60 03 8c vspltisw v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vspltisw_2>: 0000000000100008 <test_vspltisw_2>:
100008: 10 61 03 8c vspltisw v3,1 100008: 10 61 03 8c vspltisw v3,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vspltisw_3>: 0000000000100010 <test_vspltisw_3>:
100010: 10 7f 03 8c vspltisw v3,-1 100010: 10 7f 03 8c vspltisw v3,-1
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vspltisw_4>: 0000000000100018 <test_vspltisw_4>:
100018: 10 7e 03 8c vspltisw v3,-2 100018: 10 7e 03 8c vspltisw v3,-2
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_vspltw.dis
View File

@ -1,17 +1,13 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vspltw.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vspltw_1>: 0000000000100000 <test_vspltw_1>:
100000: 10 60 22 8c vspltw v3,v4,0 100000: 10 60 22 8c vspltw v3,v4,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vspltw_2>: 0000000000100008 <test_vspltw_2>:
100008: 10 61 22 8c vspltw v3,v4,1 100008: 10 61 22 8c vspltw v3,v4,1
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vspltw_3>: 0000000000100010 <test_vspltw_3>:
100010: 10 63 22 8c vspltw v3,v4,3 100010: 10 63 22 8c vspltw v3,v4,3
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vsubshs.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vsubshs.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vsubshs_1>: 0000000000100000 <test_vsubshs_1>:
100000: 10 63 27 40 .long 0x10632740 100000: 10 63 27 40 .long 0x10632740
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

8
src/xenia/cpu/frontend/test/bin/instr_vsubuhm.dis
View File

@ -1,9 +1,5 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vsubuhm.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vsubuhm_1>: 0000000000100000 <test_vsubuhm_1>:
100000: 10 63 24 40 vsubuhm v3,v3,v4 100000: 10 63 24 40 vsubuhm v3,v3,v4
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_vupkd3d128.dis
View File

@ -1,29 +1,25 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vupkd3d128.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vupkd3d128_d3dcolor>: 0000000000100000 <test_vupkd3d128_d3dcolor>:
100000: 18 60 1f f0 vupkd3d128 v3,v3,0 100000: 18 60 1f f0 vupkd3d128 v3,v3,0
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vupkd3d128_short2_0>: 0000000000100008 <test_vupkd3d128_short2_0>:
100008: 18 64 1f f0 vupkd3d128 v3,v3,4 100008: 18 64 1f f0 vupkd3d128 v3,v3,4
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr
0000000000100010 <test_vupkd3d128_short2_1>: 0000000000100010 <test_vupkd3d128_short2_1>:
100010: 18 64 1f f0 vupkd3d128 v3,v3,4 100010: 18 64 1f f0 vupkd3d128 v3,v3,4
100014: 4e 80 00 20 blr 100014: 4e 80 00 20 blr
0000000000100018 <test_vupkd3d128_short2_2>: 0000000000100018 <test_vupkd3d128_short2_2>:
100018: 18 64 1f f0 vupkd3d128 v3,v3,4 100018: 18 64 1f f0 vupkd3d128 v3,v3,4
10001c: 4e 80 00 20 blr 10001c: 4e 80 00 20 blr
0000000000100020 <test_vupkd3d128_float16_2_0>: 0000000000100020 <test_vupkd3d128_float16_2_0>:
100020: 18 6c 1f f0 vupkd3d128 v3,v3,12 100020: 18 6c 1f f0 vupkd3d128 v3,v3,12
100024: 4e 80 00 20 blr 100024: 4e 80 00 20 blr
0000000000100028 <test_vupkd3d128_float16_4_0>: 0000000000100028 <test_vupkd3d128_float16_4_0>:
100028: 18 74 1f f0 vupkd3d128 v3,v3,20 100028: 18 74 1f f0 vupkd3d128 v3,v3,20
10002c: 4e 80 00 20 blr 10002c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_vupkhsh.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vupkhsh.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vupkhsh_0>: 0000000000100000 <test_vupkhsh_0>:
100000: 10 60 1a 4e vupkhsh v3,v3 100000: 10 60 1a 4e vupkhsh v3,v3
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vupkhsh_1>: 0000000000100008 <test_vupkhsh_1>:
100008: 10 60 1a 4e vupkhsh v3,v3 100008: 10 60 1a 4e vupkhsh v3,v3
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

12
src/xenia/cpu/frontend/test/bin/instr_vupklsh.dis
View File

@ -1,13 +1,9 @@
/vagrant/src/xenia/cpu/frontend/test/bin//instr_vupklsh.o: file format elf64-powerpc
Disassembly of section .text: Disassembly of section .text:
0000000000100000 <test_vupklsh_0>: 0000000000100000 <test_vupklsh_0>:
100000: 10 60 1a ce vupklsh v3,v3 100000: 10 60 1a ce vupklsh v3,v3
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_vupklsh_1>: 0000000000100008 <test_vupklsh_1>:
100008: 10 60 1a ce vupklsh v3,v3 100008: 10 60 1a ce vupklsh v3,v3
10000c: 4e 80 00 20 blr 10000c: 4e 80 00 20 blr

66
src/xenia/cpu/frontend/test/update.sh
View File

@ -1,66 +0,0 @@
#!/bin/sh
set -e
THIS_SCRIPT_DIR=$( cd "$( dirname "$0" )" && pwd )
BINUTILS=$THIS_SCRIPT_DIR/../../../../../third_party/binutils/bin/
PPC_AS=$BINUTILS/powerpc-none-elf-as
PPC_LD=$BINUTILS/powerpc-none-elf-ld
PPC_OBJDUMP=$BINUTILS/powerpc-none-elf-objdump
PPC_NM=$BINUTILS/powerpc-none-elf-nm
BIN=$THIS_SCRIPT_DIR/bin/
if [ -d "$BIN" ]; then
rm -f $BIN/*.o
rm -f $BIN/*.dis
rm -f $BIN/*.bin
rm -f $BIN/*.map
else
mkdir -p $BIN
fi
SRCS=$THIS_SCRIPT_DIR/*.s
for SRC in $SRCS
do
SRC_NAME=$(basename $SRC)
OBJ_FILE=$BIN/${SRC_NAME%.*}.o
$PPC_AS \
-a64 \
-be \
-mregnames \
-mpower7 \
-maltivec \
-mvsx \
-mvmx128 \
-R \
-o $OBJ_FILE \
$SRC
$PPC_OBJDUMP \
--adjust-vma=0x100000 \
-Mpower7 \
-Mvmx128 \
-D \
-EB \
$OBJ_FILE \
> $BIN/${SRC_NAME%.*}.dis
$PPC_LD \
-A powerpc:common64 \
-melf64ppc \
-EB \
-nostdlib \
--oformat binary \
-Ttext 0x100000 \
-e 0x100000 \
-o $BIN/${SRC_NAME%.*}.bin \
$OBJ_FILE
$PPC_NM \
--numeric-sort \
$OBJ_FILE \
> $BIN/${SRC_NAME%.*}.map
done

1
third_party/binutils-ppc-cygwin vendored Submodule

@ -0,0 +1 @@
Subproject commit 6f3f15db908d339472db7be450f7c58bb71545cc

2
third_party/binutils/README.md vendored
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@ -4,3 +4,5 @@ mainline binutils: https://sourceware.org/ml/binutils/2007-03/msg00366.html
You can find a snapshot of 2.24 here: You can find a snapshot of 2.24 here:
http://mirrors.kernel.org/sourceware/binutils/releases/binutils-2.24.tar.gz http://mirrors.kernel.org/sourceware/binutils/releases/binutils-2.24.tar.gz
Build on cygwin with: `bash -x -o igncr build.sh`

62
xb.bat
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@ -92,6 +92,10 @@ ECHO.
ECHO xb build [--checked OR --debug OR --release] [--force] ECHO xb build [--checked OR --debug OR --release] [--force]
ECHO Initializes dependencies and prepares build environment. ECHO Initializes dependencies and prepares build environment.
ECHO. ECHO.
ECHO xb gentest
ECHO Generates test binaries (under src/xenia/cpu/frontend/test/bin/).
ECHO Run after modifying test .s files.
ECHO.
ECHO xb test [--checked OR --debug OR --release] [--continue] ECHO xb test [--checked OR --debug OR --release] [--continue]
ECHO Runs automated tests. Tests must have been built with `xb build`. ECHO Runs automated tests. Tests must have been built with `xb build`.
ECHO. ECHO.
@ -257,6 +261,64 @@ ENDLOCAL & SET _RESULT=0
GOTO :eof GOTO :eof
REM ============================================================================
REM xb gentest
REM ============================================================================
:perform_gentest
SETLOCAL EnableDelayedExpansion
ECHO Generating test binaries...
SET BINUTILS=third_party\binutils-ppc-cygwin
SET PPC_AS=%BINUTILS%\powerpc-none-elf-as.exe
SET PPC_LD=%BINUTILS%\powerpc-none-elf-ld.exe
SET PPC_OBJDUMP=%BINUTILS%\powerpc-none-elf-objdump.exe
SET PPC_NM=%BINUTILS%\powerpc-none-elf-nm.exe
SET TEST_SRC=src\xenia\cpu\frontend\test\
SET TEST_BIN=%TEST_SRC%\bin
IF NOT EXIST %TEST_BIN% (mkdir %TEST_BIN%)
SET ANY_ERRORS=0
PUSHD %TEST_SRC%
FOR %%G in (*.s) DO (
ECHO ^> generating %%~nG...
POPD
SET SRC_FILE=%TEST_SRC%\%%G
SET SRC_NAME=%%~nG
SET OBJ_FILE=%TEST_BIN%\!SRC_NAME!.o
%PPC_AS% -a64 -be -mregnames -mpower7 -maltivec -mvsx -mvmx128 -R -o !OBJ_FILE! !SRC_FILE!
IF !ERRORLEVEL! NEQ 0 (
SET ANY_ERRORS=1
)
%PPC_OBJDUMP% --adjust-vma=0x100000 -Mpower7 -Mvmx128 -D -EB !OBJ_FILE! > %TEST_BIN%\!SRC_NAME!.dis.tmp
IF !ERRORLEVEL! NEQ 0 (
SET ANY_ERRORS=1
)
REM Eat the first 4 lines to kill the file path that'll differ across machines.
MORE +4 %TEST_BIN%\!SRC_NAME!.dis.tmp > %TEST_BIN%\!SRC_NAME!.dis
DEL %TEST_BIN%\!SRC_NAME!.dis.tmp
%PPC_LD% -A powerpc:common64 -melf64ppc -EB -nostdlib --oformat binary -Ttext 0x100000 -e 0x100000 -o %TEST_BIN%\!SRC_NAME!.bin !OBJ_FILE!
IF !ERRORLEVEL! NEQ 0 (
SET ANY_ERRORS=1
)
%PPC_NM% --numeric-sort !OBJ_FILE! > %TEST_BIN%\!SRC_NAME!.map
IF !ERRORLEVEL! NEQ 0 (
SET ANY_ERRORS=1
)
PUSHD %TEST_SRC%
)
POPD
IF %ANY_ERRORS% NEQ 0 (
ECHO.
ECHO ERROR: failed to build one or more tests
ENDLOCAL & SET _RESULT=1
GOTO :eof
)
ENDLOCAL & SET _RESULT=0
GOTO :eof
REM ============================================================================ REM ============================================================================
REM xb test REM xb test
REM ============================================================================ REM ============================================================================