From 3117d737ed54a941f8045c7d8a2a065b96c4334a Mon Sep 17 00:00:00 2001
From: Parker Lamb <parkerlamb@users.noreply.github.com>
Date: Fri, 19 May 2017 13:50:48 -0500
Subject: [PATCH 1/3] PPC: Fixed padding for FormatDS instruction decode data.

---
 src/xenia/cpu/ppc/ppc_decode_data.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/xenia/cpu/ppc/ppc_decode_data.h b/src/xenia/cpu/ppc/ppc_decode_data.h
index 76ba0e2ba..60b4de431 100644
--- a/src/xenia/cpu/ppc/ppc_decode_data.h
+++ b/src/xenia/cpu/ppc/ppc_decode_data.h
@@ -86,6 +86,7 @@ struct PPCDecodeData {
     union {
       uint32_t value_;
       struct {
+        uint32_t : 2;
         uint32_t DS : 14;
         uint32_t RA : 5;
         uint32_t RT : 5;

From aab946a36b5189dacf686d800c7635389ebba1bd Mon Sep 17 00:00:00 2001
From: Parker Lamb <parkerlamb@users.noreply.github.com>
Date: Fri, 19 May 2017 14:13:03 -0500
Subject: [PATCH 2/3] PPC: Add cstdlib includes for code generated by
 ppc-table-gen.

---
 tools/ppc-table-gen | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/ppc-table-gen b/tools/ppc-table-gen
index edbacde93..b771dd1e3 100644
--- a/tools/ppc-table-gen
+++ b/tools/ppc-table-gen
@@ -137,6 +137,7 @@ def generate_opcodes(insns):
   w0('#define XENIA_CPU_PPC_PPC_OPCODE_H_')
   w0('')
   w0('#include <cstdint>')
+  w0('#include <cstdlib>')
   w0('')
   w0('namespace xe {')
   w0('namespace cpu {')
@@ -176,6 +177,7 @@ def generate_table(insns):
   w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
   w0('// clang-format off')
   w0('#include <cstdint>')
+  w0('#include <cstdlib>')
   w0('')
   w0('#include "xenia/base/assert.h"')
   w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
@@ -279,6 +281,7 @@ def generate_disasm(insns):
   w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
   w0('// clang-format off')
   w0('#include <cstdint>')
+  w0('#include <cstdlib>')
   w0('')
   w0('#include "xenia/base/assert.h"')
   w0('#include "xenia/cpu/ppc/ppc_decode_data.h"')
@@ -410,6 +413,7 @@ def generate_lookup(insns):
   w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
   w0('// clang-format off')
   w0('#include <cstdint>')
+  w0('#include <cstdlib>')
   w0('')
   w0('#include "xenia/base/assert.h"')
   w0('#include "xenia/cpu/ppc/ppc_opcode.h"')

From 4b607a68babc26231d730c982c0331084d506aed Mon Sep 17 00:00:00 2001
From: Parker Lamb <parkerlamb@users.noreply.github.com>
Date: Fri, 19 May 2017 14:14:12 -0500
Subject: [PATCH 3/3] PPC: Fix typo in instruction disassembly for mtspr.

---
 src/xenia/cpu/ppc/ppc_opcode_disasm.cc | 4 ++--
 tools/ppc-instructions.xml             | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/xenia/cpu/ppc/ppc_opcode_disasm.cc b/src/xenia/cpu/ppc/ppc_opcode_disasm.cc
index 173f89442..58742fbf7 100644
--- a/src/xenia/cpu/ppc/ppc_opcode_disasm.cc
+++ b/src/xenia/cpu/ppc/ppc_opcode_disasm.cc
@@ -1689,9 +1689,9 @@ void PrintDisasm_mtmsrd(const PPCDecodeData& d, StringBuffer* str) {
   str->AppendFormat("r%d", d.X.RS());
 }
 void PrintDisasm_mtspr(const PPCDecodeData& d, StringBuffer* str) {
-  // mtmspr [SPR], [RS]
+  // mtspr [SPR], [RS]
   size_t str_start = str->length();
-  str->Append("mtmspr");
+  str->Append("mtspr");
   PadStringBuffer(str, str_start, kNamePad);
   str->AppendFormat("%d", d.XFX.SPR());
   str->Append(", ");
diff --git a/tools/ppc-instructions.xml b/tools/ppc-instructions.xml
index 2288d75ac..e8c5e2837 100644
--- a/tools/ppc-instructions.xml
+++ b/tools/ppc-instructions.xml
@@ -908,7 +908,7 @@
   <insn mnem="mtspr"        opcode="7c0003a6" form="XFX"      group="c" desc="Move to Special-Purpose Register">
     <in field="RS" />
     <out field="SPR" />
-    <disasm>mtmspr [SPR], [RS]</disasm>
+    <disasm>mtspr [SPR], [RS]</disasm>
   </insn>
   <insn mnem="mulhdx"       opcode="7c000092" form="XO"       group="i" desc="Multiply High Doubleword">
     <in field="RA" />