diff --git a/src/alloy/frontend/ppc/ppc_emit_altivec.cc b/src/alloy/frontend/ppc/ppc_emit_altivec.cc
index 75eb13a23..381634af0 100644
--- a/src/alloy/frontend/ppc/ppc_emit_altivec.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_altivec.cc
@@ -1344,6 +1344,8 @@ XEEMITTER(vrsqrtefp128, VX128_3(6, 1648), VX128_3)(PPCHIRBuilder& f,
 
 int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                     uint32_t vc) {
+  // For each bit:
+  // VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
   Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
   f.StoreVR(vd, v);
   return 0;
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.bin b/src/alloy/frontend/ppc/test/bin/instr_vsel.bin
new file mode 100644
index 000000000..c62e03541
Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vsel.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.dis b/src/alloy/frontend/ppc/test/bin/instr_vsel.dis
new file mode 100644
index 000000000..60fb62fce
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vsel.dis
@@ -0,0 +1,17 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsel.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vsel_1>:
+  100000:	10 a3 21 6a 	vsel    v5,v3,v4,v5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vsel_2>:
+  100008:	10 a3 21 6a 	vsel    v5,v3,v4,v5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vsel_3>:
+  100010:	10 a3 21 6a 	vsel    v5,v3,v4,v5
+  100014:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vsel.map b/src/alloy/frontend/ppc/test/bin/instr_vsel.map
new file mode 100644
index 000000000..41f9acf96
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vsel.map
@@ -0,0 +1,3 @@
+0000000000000000 t test_vsel_1
+0000000000000008 t test_vsel_2
+0000000000000010 t test_vsel_3
diff --git a/src/alloy/frontend/ppc/test/instr_vsel.s b/src/alloy/frontend/ppc/test/instr_vsel.s
new file mode 100644
index 000000000..7a8863ca1
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_vsel.s
@@ -0,0 +1,29 @@
+test_vsel_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vsel_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
+
+test_vsel_3:
+  #_ REGISTER_IN v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_IN v5 [10101010, 10101010, 10101010, 10101010]
+  vsel v5, v3, v4, v5
+  blr
+  #_ REGISTER_OUT v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
+  #_ REGISTER_OUT v5 [1C111213, 14151617, 18191A1B, 1C1D1E1F]