diff --git a/src/alloy/compiler/passes/control_flow_analysis_pass.cc b/src/alloy/compiler/passes/control_flow_analysis_pass.cc index 89442bcb6..bff651fe2 100644 --- a/src/alloy/compiler/passes/control_flow_analysis_pass.cc +++ b/src/alloy/compiler/passes/control_flow_analysis_pass.cc @@ -43,17 +43,16 @@ int ControlFlowAnalysisPass::Run(HIRBuilder* builder) { while (block) { auto instr = block->instr_tail; while (instr) { - if (instr->opcode->flags & OPCODE_FLAG_BRANCH) { - if (instr->opcode == &OPCODE_BRANCH_info) { - auto label = instr->src1.label; - builder->AddEdge(block, label->block, Edge::UNCONDITIONAL); - break; - } else if (instr->opcode == &OPCODE_BRANCH_TRUE_info || - instr->opcode == &OPCODE_BRANCH_FALSE_info) { - auto label = instr->src2.label; - builder->AddEdge(block, label->block, 0); - break; - } + if ((instr->opcode->flags & OPCODE_FLAG_BRANCH) == 0) { + break; + } + if (instr->opcode == &OPCODE_BRANCH_info) { + auto label = instr->src1.label; + builder->AddEdge(block, label->block, Edge::UNCONDITIONAL); + } else if (instr->opcode == &OPCODE_BRANCH_TRUE_info || + instr->opcode == &OPCODE_BRANCH_FALSE_info) { + auto label = instr->src2.label; + builder->AddEdge(block, label->block, 0); } instr = instr->prev; } diff --git a/src/alloy/compiler/passes/data_flow_analysis_pass.cc b/src/alloy/compiler/passes/data_flow_analysis_pass.cc index 8501d1675..b4e1ea644 100644 --- a/src/alloy/compiler/passes/data_flow_analysis_pass.cc +++ b/src/alloy/compiler/passes/data_flow_analysis_pass.cc @@ -82,7 +82,7 @@ void DataFlowAnalysisPass::AnalyzeFlow(HIRBuilder* builder, // Walk blocks in reverse and calculate incoming/outgoing values. auto block = builder->last_block(); while (block) { - // allocate bitsets based on max value number + // Allocate bitsets based on max value number. block->incoming_values = incoming_bitvectors[block->ordinal]; auto& incoming_values = *block->incoming_values;