diff --git a/src/xenia/cpu/frontend/test/instr_srw.s b/src/xenia/cpu/frontend/test/instr_srw.s index 874035416..dd9c033cc 100644 --- a/src/xenia/cpu/frontend/test/instr_srw.s +++ b/src/xenia/cpu/frontend/test/instr_srw.s @@ -7,6 +7,15 @@ test_srw_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0 +test_srw_1_constant: + li r4, 1 + li r5, 0 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + test_srw_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -16,6 +25,15 @@ test_srw_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0 +test_srw_2_constant: + li r4, -1 + li r5, 0 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + test_srw_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -25,6 +43,15 @@ test_srw_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_srw_3_constant: + li r4, -1 + li r5, 1 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000007FFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_srw_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -34,6 +61,15 @@ test_srw_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 63 +test_srw_4_constant: + li r4, -1 + li r5, 63 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + test_srw_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -43,6 +79,15 @@ test_srw_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 64 +test_srw_5_constant: + li r4, -1 + li r5, 64 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + test_srw_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -52,6 +97,15 @@ test_srw_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 100 +test_srw_6_constant: + li r4, -1 + li r5, 100 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + test_srw_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 30 @@ -61,6 +115,15 @@ test_srw_7: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 30 +test_srw_7_constant: + li r4, -1 + li r5, 30 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000003 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + test_srw_8: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 31 @@ -70,6 +133,15 @@ test_srw_8: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 31 +test_srw_8_constant: + li r4, -1 + li r5, 31 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + test_srw_9: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 32 @@ -78,3 +150,12 @@ test_srw_9: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 32 + +test_srw_9_constant: + li r4, -1 + li r5, 32 + srw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32 diff --git a/src/xenia/cpu/frontend/test/instr_stvew.s b/src/xenia/cpu/frontend/test/instr_stvew.s index ec13b25e2..d342c57b7 100644 --- a/src/xenia/cpu/frontend/test/instr_stvew.s +++ b/src/xenia/cpu/frontend/test/instr_stvew.s @@ -8,6 +8,16 @@ test_stvew_1: #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC +test_stvew_1_constant: + #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC + li r4, 0x1050 + #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + stvewx v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x1050 + #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + #_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC + test_stvew_2: #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ REGISTER_IN r4 0x1054 @@ -18,6 +28,16 @@ test_stvew_2: #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC +test_stvew_2_constant: + #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC + li r4, 0x1054 + #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + stvewx v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x1054 + #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + #_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC + test_stvew_3: #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ REGISTER_IN r4 0x1058 @@ -28,6 +48,16 @@ test_stvew_3: #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC +test_stvew_3_constant: + #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC + li r4, 0x1058 + #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + stvewx v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x1058 + #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC + test_stvew_4: #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ REGISTER_IN r4 0x105C @@ -37,3 +67,13 @@ test_stvew_4: #_ REGISTER_OUT r4 0x105C #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F + +test_stvew_4_constant: + #_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC + li r4, 0x105C + #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + stvewx v3, r0, r4 + blr + #_ REGISTER_OUT r4 0x105C + #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] + #_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F diff --git a/src/xenia/cpu/frontend/test/instr_stvl.s b/src/xenia/cpu/frontend/test/instr_stvl.s index ce1dfef01..1b0570287 100644 --- a/src/xenia/cpu/frontend/test/instr_stvl.s +++ b/src/xenia/cpu/frontend/test/instr_stvl.s @@ -8,6 +8,16 @@ test_stvl_1: #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F +test_stvl_1_constant: + #_ MEMORY_IN 00001040 00000000 00000000 00000000 3F800000 + li r4, 0x1040 + #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] + stvlx v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1040 + #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] + #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F + test_stvl_2: #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ REGISTER_IN r4 0x1044 @@ -17,3 +27,13 @@ test_stvl_2: #_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB + +test_stvl_2_constant: + #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F + li r4, 0x1044 + #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] + stvlx v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1044 + #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] + #_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB diff --git a/src/xenia/cpu/frontend/test/instr_stvr.s b/src/xenia/cpu/frontend/test/instr_stvr.s index a651f0ba0..ad0844c11 100644 --- a/src/xenia/cpu/frontend/test/instr_stvr.s +++ b/src/xenia/cpu/frontend/test/instr_stvr.s @@ -12,6 +12,20 @@ test_stvr_1: #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000 +test_stvr_1_constant: + #_ MEMORY_IN 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F + #_ MEMORY_IN 00001050 00000000 00000000 00000000 00000000 + li r4, 0x1040 + li r5, 0x10 + #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] + stvrx v3, r4, r5 + blr + #_ REGISTER_OUT r4 0x1040 + #_ REGISTER_OUT r5 0x10 + #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] + #_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F + #_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000 + test_stvr_2: #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ REGISTER_IN r4 0x1044 @@ -21,3 +35,13 @@ test_stvr_2: #_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F + +test_stvr_2_constant: + #_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F + li r4, 0x1044 + #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] + stvrx v3, r4, r0 + blr + #_ REGISTER_OUT r4 0x1044 + #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] + #_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F diff --git a/src/xenia/cpu/frontend/test/instr_subf.s b/src/xenia/cpu/frontend/test/instr_subf.s index c9fce05a7..3ad052abe 100644 --- a/src/xenia/cpu/frontend/test/instr_subf.s +++ b/src/xenia/cpu/frontend/test/instr_subf.s @@ -7,6 +7,17 @@ test_subf_1: #_ REGISTER_OUT r11 0x00000000000103C0 #_ REGISTER_OUT r3 0x1 +test_subf_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + lis r11, 1 + ori r11, r11, 0x03C0 + subf r3, r10, r11 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r11 0x00000000000103C0 + #_ REGISTER_OUT r3 0x1 + test_subf_2: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 0 @@ -16,6 +27,15 @@ test_subf_2: #_ REGISTER_OUT r11 0 #_ REGISTER_OUT r3 0 +test_subf_2_constant: + li r10, 0 + li r11, 0 + subf r3, r10, r11 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 0 + test_subf_3: #_ REGISTER_IN r10 1 #_ REGISTER_IN r11 0 @@ -25,6 +45,15 @@ test_subf_3: #_ REGISTER_OUT r11 0 #_ REGISTER_OUT r3 -1 +test_subf_3_constant: + li r10, 1 + li r11, 0 + subf r3, r10, r11 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 -1 + test_subf_4: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 1 @@ -34,6 +63,15 @@ test_subf_4: #_ REGISTER_OUT r11 1 #_ REGISTER_OUT r3 1 +test_subf_4_constant: + li r10, 0 + li r11, 1 + subf r3, r10, r11 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 1 + #_ REGISTER_OUT r3 1 + test_subf_5: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF @@ -42,3 +80,12 @@ test_subf_5: #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0x0 + +test_subf_5_constant: + li r10, -1 + li r11, -1 + subf r3, r10, r11 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0x0 diff --git a/src/xenia/cpu/frontend/test/instr_subfc.s b/src/xenia/cpu/frontend/test/instr_subfc.s index e16b2f709..84dc25dd4 100644 --- a/src/xenia/cpu/frontend/test/instr_subfc.s +++ b/src/xenia/cpu/frontend/test/instr_subfc.s @@ -9,6 +9,19 @@ test_subfc_1: #_ REGISTER_OUT r3 1 #_ REGISTER_OUT r4 1 +test_subfc_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + lis r11, 1 + ori r11, r11, 0x03C0 + subfc r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r11 0x00000000000103C0 + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + test_subfc_2: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 0 @@ -20,6 +33,17 @@ test_subfc_2: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 +test_subfc_2_constant: + li r10, 0 + li r11, 0 + subfc r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + test_subfc_3: #_ REGISTER_IN r10 1 #_ REGISTER_IN r11 0 @@ -31,6 +55,17 @@ test_subfc_3: #_ REGISTER_OUT r3 -1 #_ REGISTER_OUT r4 0 +test_subfc_3_constant: + li r10, 1 + li r11, 0 + subfc r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 0 + test_subfc_4: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 1 @@ -42,6 +77,17 @@ test_subfc_4: #_ REGISTER_OUT r3 1 #_ REGISTER_OUT r4 1 +test_subfc_4_constant: + li r10, 0 + li r11, 1 + subfc r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 1 + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + test_subfc_5: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF @@ -52,3 +98,14 @@ test_subfc_5: #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 + +test_subfc_5_constant: + li r10, -1 + li r11, -1 + subfc r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 diff --git a/src/xenia/cpu/frontend/test/instr_subfe.s b/src/xenia/cpu/frontend/test/instr_subfe.s index 460b32987..25b4891ae 100644 --- a/src/xenia/cpu/frontend/test/instr_subfe.s +++ b/src/xenia/cpu/frontend/test/instr_subfe.s @@ -9,6 +9,19 @@ test_subfe_1: #_ REGISTER_OUT r3 0x0 #_ REGISTER_OUT r4 1 +test_subfe_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + lis r11, 1 + ori r11, r11, 0x03C0 + subfe r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r11 0x00000000000103C0 + #_ REGISTER_OUT r3 0x0 + #_ REGISTER_OUT r4 1 + test_subfe_2: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 0 @@ -20,6 +33,17 @@ test_subfe_2: #_ REGISTER_OUT r3 0xffffffffffffffff #_ REGISTER_OUT r4 0 +test_subfe_2_constant: + li r10, 0 + li r11, 0 + subfe r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0 + test_subfe_3: #_ REGISTER_IN r10 1 #_ REGISTER_IN r11 0 @@ -31,6 +55,17 @@ test_subfe_3: #_ REGISTER_OUT r3 0xfffffffffffffffe #_ REGISTER_OUT r4 0 +test_subfe_3_constant: + li r10, 1 + li r11, 0 + subfe r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 0 + test_subfe_4: #_ REGISTER_IN r10 0 #_ REGISTER_IN r11 1 @@ -42,6 +77,17 @@ test_subfe_4: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 +test_subfe_4_constant: + li r10, 0 + li r11, 1 + subfe r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r11 1 + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + test_subfe_5: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF @@ -52,3 +98,14 @@ test_subfe_5: #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r4 0 + +test_subfe_5_constant: + li r10, -1 + li r11, -1 + subfe r3, r10, r11 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0 diff --git a/src/xenia/cpu/frontend/test/instr_subfic.s b/src/xenia/cpu/frontend/test/instr_subfic.s index 32fac1c6f..3a958eb21 100644 --- a/src/xenia/cpu/frontend/test/instr_subfic.s +++ b/src/xenia/cpu/frontend/test/instr_subfic.s @@ -7,6 +7,16 @@ test_subfic_1: #_ REGISTER_OUT r3 0xffffffffffff0001 #_ REGISTER_OUT r4 0 +test_subfic_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + subfic r3, r10, 0x3C0 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xffffffffffff0001 + #_ REGISTER_OUT r4 0 + test_subfic_2: #_ REGISTER_IN r10 0x00000000000103BF subfic r3, r10, -234 @@ -16,6 +26,16 @@ test_subfic_2: #_ REGISTER_OUT r3 0xfffffffffffefb57 #_ REGISTER_OUT r4 1 +test_subfic_2_constant: + lis r10, 1 + ori r10, r10, 0x03BF + subfic r3, r10, -234 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xfffffffffffefb57 + #_ REGISTER_OUT r4 1 + test_subfic_3: #_ REGISTER_IN r10 0 subfic r3, r10, 0 @@ -25,6 +45,15 @@ test_subfic_3: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 +test_subfic_3_constant: + li r10, 0 + subfic r3, r10, 0 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + test_subfic_4: #_ REGISTER_IN r10 1 subfic r3, r10, 0 @@ -34,6 +63,15 @@ test_subfic_4: #_ REGISTER_OUT r3 -1 #_ REGISTER_OUT r4 0 +test_subfic_4_constant: + li r10, 1 + subfic r3, r10, 0 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 0 + test_subfic_5: #_ REGISTER_IN r10 0 subfic r3, r10, 1 @@ -43,6 +81,15 @@ test_subfic_5: #_ REGISTER_OUT r3 1 #_ REGISTER_OUT r4 1 +test_subfic_5_constant: + li r10, 0 + subfic r3, r10, 1 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + test_subfic_6: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF subfic r3, r10, -1 @@ -51,3 +98,12 @@ test_subfic_6: #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 + +test_subfic_6_constant: + li r10, -1 + subfic r3, r10, -1 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 diff --git a/src/xenia/cpu/frontend/test/instr_subfme.s b/src/xenia/cpu/frontend/test/instr_subfme.s index 37cce8886..9366b7e3f 100644 --- a/src/xenia/cpu/frontend/test/instr_subfme.s +++ b/src/xenia/cpu/frontend/test/instr_subfme.s @@ -10,6 +10,19 @@ test_subfme_one_ca_1: #_ REGISTER_OUT r3 0xfffffffffffefc40 #_ REGISTER_OUT r4 1 +test_subfme_one_ca_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xfffffffffffefc40 + #_ REGISTER_OUT r4 1 + test_subfme_one_ca_2: #_ REGISTER_IN r10 0 xor r3, r3, r3 @@ -22,6 +35,18 @@ test_subfme_one_ca_2: #_ REGISTER_OUT r3 -1 #_ REGISTER_OUT r4 1 +test_subfme_one_ca_2_constant: + li r10, 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 1 + test_subfme_one_ca_3: #_ REGISTER_IN r10 1 xor r3, r3, r3 @@ -34,6 +59,18 @@ test_subfme_one_ca_3: #_ REGISTER_OUT r3 0xfffffffffffffffe #_ REGISTER_OUT r4 1 +test_subfme_one_ca_3_constant: + li r10, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 1 + test_subfme_one_ca_4: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -46,6 +83,18 @@ test_subfme_one_ca_4: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 +test_subfme_one_ca_4_constant: + li r10, -1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + test_subfme_zero_ca_1: #_ REGISTER_IN r10 0x00000000000103BF xor r3, r3, r3 @@ -57,6 +106,18 @@ test_subfme_zero_ca_1: #_ REGISTER_OUT r3 0xfffffffffffefc3f #_ REGISTER_OUT r4 1 +test_subfme_zero_ca_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + xor r3, r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xfffffffffffefc3f + #_ REGISTER_OUT r4 1 + test_subfme_zero_ca_2: #_ REGISTER_IN r10 0 xor r3, r3, r3 @@ -68,6 +129,17 @@ test_subfme_zero_ca_2: #_ REGISTER_OUT r3 0xfffffffffffffffe #_ REGISTER_OUT r4 1 +test_subfme_zero_ca_2_constant: + li r10, 0 + xor r3, r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 1 + test_subfme_zero_ca_3: #_ REGISTER_IN r10 1 xor r3, r3, r3 @@ -79,6 +151,17 @@ test_subfme_zero_ca_3: #_ REGISTER_OUT r3 0xfffffffffffffffd #_ REGISTER_OUT r4 1 +test_subfme_zero_ca_3_constant: + li r10, 1 + xor r3, r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r3 0xfffffffffffffffd + #_ REGISTER_OUT r4 1 + test_subfme_zero_ca_4: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -89,3 +172,14 @@ test_subfme_zero_ca_4: #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0xffffffffffffffff #_ REGISTER_OUT r4 0 + +test_subfme_zero_ca_4_constant: + li r10, -1 + xor r3, r3, r3 + addic r3, r3, 1 + subfme r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0 diff --git a/src/xenia/cpu/frontend/test/instr_subfze.s b/src/xenia/cpu/frontend/test/instr_subfze.s index 127291a8b..d050dce3e 100644 --- a/src/xenia/cpu/frontend/test/instr_subfze.s +++ b/src/xenia/cpu/frontend/test/instr_subfze.s @@ -10,6 +10,19 @@ test_subfze_one_ca_1: #_ REGISTER_OUT r3 0xfffffffffffefc41 #_ REGISTER_OUT r4 0 +test_subfze_one_ca_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xfffffffffffefc41 + #_ REGISTER_OUT r4 0 + test_subfze_one_ca_2: #_ REGISTER_IN r10 0 xor r3, r3, r3 @@ -22,6 +35,18 @@ test_subfze_one_ca_2: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 1 +test_subfze_one_ca_2_constant: + li r10, 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + test_subfze_one_ca_3: #_ REGISTER_IN r10 1 xor r3, r3, r3 @@ -34,6 +59,18 @@ test_subfze_one_ca_3: #_ REGISTER_OUT r3 -1 #_ REGISTER_OUT r4 0 +test_subfze_one_ca_3_constant: + li r10, 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 0 + test_subfze_one_ca_4: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -46,6 +83,18 @@ test_subfze_one_ca_4: #_ REGISTER_OUT r3 0x1 #_ REGISTER_OUT r4 0 +test_subfze_one_ca_4_constant: + li r10, -1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0x1 + #_ REGISTER_OUT r4 0 + test_subfze_zero_ca_1: #_ REGISTER_IN r10 0x00000000000103BF xor r3, r3, r3 @@ -57,6 +106,18 @@ test_subfze_zero_ca_1: #_ REGISTER_OUT r3 0xfffffffffffefc40 #_ REGISTER_OUT r4 0 +test_subfze_zero_ca_1_constant: + lis r10, 1 + ori r10, r10, 0x03BF + xor r3, r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0x00000000000103BF + #_ REGISTER_OUT r3 0xfffffffffffefc40 + #_ REGISTER_OUT r4 0 + test_subfze_zero_ca_2: #_ REGISTER_IN r10 0 xor r3, r3, r3 @@ -68,6 +129,17 @@ test_subfze_zero_ca_2: #_ REGISTER_OUT r3 0xffffffffffffffff #_ REGISTER_OUT r4 0 +test_subfze_zero_ca_2_constant: + li r10, 0 + xor r3, r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0 + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0 + test_subfze_zero_ca_3: #_ REGISTER_IN r10 1 xor r3, r3, r3 @@ -79,6 +151,17 @@ test_subfze_zero_ca_3: #_ REGISTER_OUT r3 0xfffffffffffffffe #_ REGISTER_OUT r4 0 +test_subfze_zero_ca_3_constant: + li r10, 1 + xor r3, r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 1 + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 0 + test_subfze_zero_ca_4: #_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF xor r3, r3, r3 @@ -89,3 +172,14 @@ test_subfze_zero_ca_4: #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0 + +test_subfze_zero_ca_4_constant: + li r10, -1 + xor r3, r3, r3 + addic r3, r3, 1 + subfze r3, r10 + adde r4, r0, r0 + blr + #_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0