diff --git a/src/xenia/cpu/frontend/test/instr_rldicr.s b/src/xenia/cpu/frontend/test/instr_rldicr.s index 6a249b23a..f001e5d21 100644 --- a/src/xenia/cpu/frontend/test/instr_rldicr.s +++ b/src/xenia/cpu/frontend/test/instr_rldicr.s @@ -1,3 +1,13 @@ +.macro make_test_constant dest + lis \dest, 0x0123 + ori \dest, \dest, 0x4567 + sldi \dest, \dest, 32 + lis r3, 0x89AB + ori r3, r3, 0xCDEF + clrldi r3, r3, 32 + or \dest, \dest, r3 +.endm + test_rldicr_1: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 24, 0 @@ -5,6 +15,13 @@ test_rldicr_1: #_ REGISTER_OUT r3 0x0000000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_1_constant: + make_test_constant r4 + rldicr r3, r4, 24, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_2: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 24, 8 @@ -12,6 +29,13 @@ test_rldicr_2: #_ REGISTER_OUT r3 0x6780000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_2_constant: + make_test_constant r4 + rldicr r3, r4, 24, 8 + blr + #_ REGISTER_OUT r3 0x6780000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_3: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 24, 63 @@ -19,6 +43,13 @@ test_rldicr_3: #_ REGISTER_OUT r3 0x6789abcdef012345 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_3_constant: + make_test_constant r4 + rldicr r3, r4, 24, 63 + blr + #_ REGISTER_OUT r3 0x6789abcdef012345 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_4: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 0, 0 @@ -26,6 +57,13 @@ test_rldicr_4: #_ REGISTER_OUT r3 0x0000000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_4_constant: + make_test_constant r4 + rldicr r3, r4, 0, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_5: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 0, 63 @@ -33,6 +71,13 @@ test_rldicr_5: #_ REGISTER_OUT r3 0x0123456789abcdef #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_5_constant: + make_test_constant r4 + rldicr r3, r4, 0, 63 + blr + #_ REGISTER_OUT r3 0x0123456789abcdef + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_6: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 0, 8 @@ -40,6 +85,13 @@ test_rldicr_6: #_ REGISTER_OUT r3 0x0100000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_6_constant: + make_test_constant r4 + rldicr r3, r4, 0, 8 + blr + #_ REGISTER_OUT r3 0x0100000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_7: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 63, 0 @@ -47,6 +99,13 @@ test_rldicr_7: #_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_7_constant: + make_test_constant r4 + rldicr r3, r4, 63, 0 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_8: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 63, 63 @@ -54,6 +113,13 @@ test_rldicr_8: #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_8_constant: + make_test_constant r4 + rldicr r3, r4, 63, 63 + blr + #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_rldicr_9: #_ REGISTER_IN r4 0x0123456789ABCDEF rldicr r3, r4, 31, 0 @@ -61,6 +127,13 @@ test_rldicr_9: #_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_rldicr_9_constant: + make_test_constant r4 + rldicr r3, r4, 31, 0 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_sldi_1: #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x0123456789ABCDEF @@ -70,6 +143,15 @@ test_sldi_1: #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r4 0x0123456789ABCDEF +test_sldi_1_constant: + make_test_constant r4 + li r3, -1 + sldi r3, r3, 0 + sldi r4, r4, 0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x0123456789ABCDEF + test_sldi_2: #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x0123456789ABCDEF @@ -79,6 +161,15 @@ test_sldi_2: #_ REGISTER_OUT r3 0xfffffffffffffffe #_ REGISTER_OUT r4 0x02468acf13579bde +test_sldi_2_constant: + make_test_constant r4 + li r3, -1 + sldi r3, r3, 1 + sldi r4, r4, 1 + blr + #_ REGISTER_OUT r3 0xfffffffffffffffe + #_ REGISTER_OUT r4 0x02468acf13579bde + test_sldi_3: #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x0123456789ABCDEF @@ -88,6 +179,15 @@ test_sldi_3: #_ REGISTER_OUT r3 0xffffffff00000000 #_ REGISTER_OUT r4 0x89abcdef00000000 +test_sldi_3_constant: + make_test_constant r4 + li r3, -1 + sldi r3, r3, 32 + sldi r4, r4, 32 + blr + #_ REGISTER_OUT r3 0xffffffff00000000 + #_ REGISTER_OUT r4 0x89abcdef00000000 + test_sldi_4: #_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r4 0x0123456789ABCDEF @@ -96,3 +196,12 @@ test_sldi_4: blr #_ REGISTER_OUT r3 0x8000000000000000 #_ REGISTER_OUT r4 0x8000000000000000 + +test_sldi_4_constant: + make_test_constant r4 + li r3, -1 + sldi r3, r3, 63 + sldi r4, r4, 63 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x8000000000000000 diff --git a/src/xenia/cpu/frontend/test/instr_rlwimi.s b/src/xenia/cpu/frontend/test/instr_rlwimi.s index 95db67005..7f1fc2ddf 100644 --- a/src/xenia/cpu/frontend/test/instr_rlwimi.s +++ b/src/xenia/cpu/frontend/test/instr_rlwimi.s @@ -1,3 +1,13 @@ +.macro make_test_constant dest, a, b, c, d + lis \dest, \a + ori \dest, \dest, \b + sldi \dest, \dest, 32 + lis r3, \c + ori r3, r3, \d + clrldi r3, r3, 32 + or \dest, \dest, r3 +.endm + test_rlwimi: #_ REGISTER_IN r4 0xCAFEBABE90003000 #_ REGISTER_IN r6 0xDEADBEEF00000003 @@ -5,3 +15,11 @@ test_rlwimi: blr #_ REGISTER_OUT r4 0xCAFEBABE90003000 #_ REGISTER_OUT r6 0xDEADBEEF4000C003 + +test_rlwimi_constant: + make_test_constant r4, 0xCAFE, 0xBABE, 0x9000, 0x3000 + make_test_constant r6, 0xDEAD, 0xBEEF, 0x0000, 0x0003 + rlwimi r6, r4, 2, 0, 0x1D + blr + #_ REGISTER_OUT r4 0xCAFEBABE90003000 + #_ REGISTER_OUT r6 0xDEADBEEF4000C003 diff --git a/src/xenia/cpu/frontend/test/instr_rlwinm.s b/src/xenia/cpu/frontend/test/instr_rlwinm.s index ce61c9ea4..e4401481a 100644 --- a/src/xenia/cpu/frontend/test/instr_rlwinm.s +++ b/src/xenia/cpu/frontend/test/instr_rlwinm.s @@ -7,6 +7,15 @@ test_rlwinm_extrwi: #_ REGISTER_OUT r5 0x30 #_ REGISTER_OUT r7 0x06 +test_rlwinm_extrwi_constant: + # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31 + li r5, 0x30 + # rlwinm r7, r5, 29, 28, 31 + extrwi r7, r5, 4, 25 + blr + #_ REGISTER_OUT r5 0x30 + #_ REGISTER_OUT r7 0x06 + test_rlwinm_1: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 24, 8, 15 @@ -14,6 +23,14 @@ test_rlwinm_1: #_ REGISTER_OUT r3 0x00120000 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_1_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 24, 8, 15 + blr + #_ REGISTER_OUT r3 0x00120000 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_2: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 4, 0, 27 @@ -21,6 +38,14 @@ test_rlwinm_2: #_ REGISTER_OUT r3 0x23456780 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_2_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 4, 0, 27 + blr + #_ REGISTER_OUT r3 0x23456780 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_3: #_ REGISTER_IN r4 0x90003000 rlwinm r3, r4, 2, 0, 0x1D @@ -28,6 +53,15 @@ test_rlwinm_3: #_ REGISTER_OUT r3 0x4000C000 #_ REGISTER_OUT r4 0x90003000 +test_rlwinm_3_constant: + lis r4, 0x9000 + ori r4, r4, 0x3000 + clrldi r4, r4, 32 + rlwinm r3, r4, 2, 0, 0x1D + blr + #_ REGISTER_OUT r3 0x4000C000 + #_ REGISTER_OUT r4 0x90003000 + test_rlwinm_4: #_ REGISTER_IN r4 0xB0043000 rlwinm. r3, r4, 2, 0, 0x1D @@ -36,6 +70,16 @@ test_rlwinm_4: #_ REGISTER_OUT r4 0xB0043000 # CRF = 0x8 +test_rlwinm_4_constant: + lis r4, 0xB004 + ori r4, r4, 0x3000 + clrldi r4, r4, 32 + rlwinm. r3, r4, 2, 0, 0x1D + blr + #_ REGISTER_OUT r3 0xC010C000 + #_ REGISTER_OUT r4 0xB0043000 + # CRF = 0x8 + test_rlwinm_5: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 0, 5, 0x1D @@ -43,6 +87,14 @@ test_rlwinm_5: #_ REGISTER_OUT r3 0x02345678 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_5_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 0, 5, 0x1D + blr + #_ REGISTER_OUT r3 0x02345678 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_6: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 0, 0, 31 @@ -50,6 +102,14 @@ test_rlwinm_6: #_ REGISTER_OUT r3 0x12345678 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_6_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 0, 0, 31 + blr + #_ REGISTER_OUT r3 0x12345678 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_7: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 0, 0, 16 @@ -57,6 +117,14 @@ test_rlwinm_7: #_ REGISTER_OUT r3 0x12340000 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_7_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 0, 0, 16 + blr + #_ REGISTER_OUT r3 0x12340000 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_8: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 0, 16, 31 @@ -64,9 +132,25 @@ test_rlwinm_8: #_ REGISTER_OUT r3 0x00005678 #_ REGISTER_OUT r4 0x12345678 +test_rlwinm_8_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 0, 16, 31 + blr + #_ REGISTER_OUT r3 0x00005678 + #_ REGISTER_OUT r4 0x12345678 + test_rlwinm_9: #_ REGISTER_IN r4 0x12345678 rlwinm r3, r4, 16, 16, 31 blr #_ REGISTER_OUT r3 0x00001234 #_ REGISTER_OUT r4 0x12345678 + +test_rlwinm_9_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + rlwinm r3, r4, 16, 16, 31 + blr + #_ REGISTER_OUT r3 0x00001234 + #_ REGISTER_OUT r4 0x12345678 diff --git a/src/xenia/cpu/frontend/test/instr_rlwnm.s b/src/xenia/cpu/frontend/test/instr_rlwnm.s index ae582c369..6406996e6 100644 --- a/src/xenia/cpu/frontend/test/instr_rlwnm.s +++ b/src/xenia/cpu/frontend/test/instr_rlwnm.s @@ -7,6 +7,16 @@ test_rlwnm_1: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 24 +test_rlwnm_1_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 24 + rlwnm r3, r4, r5, 8, 15 + blr + #_ REGISTER_OUT r3 0x00120000 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 24 + test_rlwnm_2: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 4 @@ -16,6 +26,16 @@ test_rlwnm_2: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 4 +test_rlwnm_2_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 4 + rlwnm r3, r4, r5, 0, 27 + blr + #_ REGISTER_OUT r3 0x23456780 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 4 + test_rlwnm_3: #_ REGISTER_IN r4 0x90003000 #_ REGISTER_IN r5 2 @@ -25,6 +45,17 @@ test_rlwnm_3: #_ REGISTER_OUT r4 0x90003000 #_ REGISTER_OUT r5 2 +test_rlwnm_3_constant: + lis r4, 0x9000 + ori r4, r4, 0x3000 + clrldi r4, r4, 32 + li r5, 2 + rlwnm r3, r4, r5, 0, 0x1D + blr + #_ REGISTER_OUT r3 0x4000C000 + #_ REGISTER_OUT r4 0x90003000 + #_ REGISTER_OUT r5 2 + test_rlwnm_4: #_ REGISTER_IN r4 0xB0043000 #_ REGISTER_IN r5 2 @@ -35,6 +66,18 @@ test_rlwnm_4: #_ REGISTER_OUT r5 2 # CRF = 0x8 +test_rlwnm_4_constant: + lis r4, 0xB004 + ori r4, r4, 0x3000 + clrldi r4, r4, 32 + li r5, 2 + rlwnm. r3, r4, r5, 0, 0x1D + blr + #_ REGISTER_OUT r3 0xC010C000 + #_ REGISTER_OUT r4 0xB0043000 + #_ REGISTER_OUT r5 2 + # CRF = 0x8 + test_rlwnm_5: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 0 @@ -44,6 +87,16 @@ test_rlwnm_5: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 0 +test_rlwnm_5_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 0 + rlwnm r3, r4, r5, 5, 0x1D + blr + #_ REGISTER_OUT r3 0x02345678 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 0 + test_rlwnm_6: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 0 @@ -53,6 +106,16 @@ test_rlwnm_6: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 0 +test_rlwnm_6_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 0 + rlwnm r3, r4, r5, 0, 31 + blr + #_ REGISTER_OUT r3 0x12345678 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 0 + test_rlwnm_7: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 0 @@ -62,6 +125,16 @@ test_rlwnm_7: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 0 +test_rlwnm_7_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 0 + rlwnm r3, r4, r5, 0, 16 + blr + #_ REGISTER_OUT r3 0x12340000 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 0 + test_rlwnm_8: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 0 @@ -71,6 +144,16 @@ test_rlwnm_8: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 0 +test_rlwnm_8_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 0 + rlwnm r3, r4, r5, 16, 31 + blr + #_ REGISTER_OUT r3 0x00005678 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 0 + test_rlwnm_9: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 16 @@ -80,6 +163,16 @@ test_rlwnm_9: #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 16 +test_rlwnm_9_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 16 + rlwnm r3, r4, r5, 16, 31 + blr + #_ REGISTER_OUT r3 0x00001234 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 16 + test_rlwnm_10: #_ REGISTER_IN r4 0x12345678 #_ REGISTER_IN r5 32 @@ -88,3 +181,13 @@ test_rlwnm_10: #_ REGISTER_OUT r3 0x12345678 #_ REGISTER_OUT r4 0x12345678 #_ REGISTER_OUT r5 32 + +test_rlwnm_10_constant: + lis r4, 0x1234 + ori r4, r4, 0x5678 + li r5, 32 + rlwnm r3, r4, r5, 0, 31 + blr + #_ REGISTER_OUT r3 0x12345678 + #_ REGISTER_OUT r4 0x12345678 + #_ REGISTER_OUT r5 32 diff --git a/src/xenia/cpu/frontend/test/instr_sld.s b/src/xenia/cpu/frontend/test/instr_sld.s index a0c525043..0ed67d1fd 100644 --- a/src/xenia/cpu/frontend/test/instr_sld.s +++ b/src/xenia/cpu/frontend/test/instr_sld.s @@ -7,6 +7,15 @@ test_sld_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0 +test_sld_1_constant: + li r4, 1 + li r5, 0 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + test_sld_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -16,6 +25,15 @@ test_sld_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0 +test_sld_2_constant: + li r4, -1 + li r5, 0 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + test_sld_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -25,6 +43,15 @@ test_sld_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_sld_3_constant: + li r4, -1 + li r5, 1 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_sld_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 62 @@ -34,6 +61,15 @@ test_sld_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 62 +test_sld_4_constant: + li r4, -1 + li r5, 62 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xc000000000000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + test_sld_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -43,6 +79,15 @@ test_sld_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 63 +test_sld_5_constant: + li r4, -1 + li r5, 63 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + test_sld_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -52,6 +97,15 @@ test_sld_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 64 +test_sld_6_constant: + li r4, -1 + li r5, 64 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + test_sld_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -60,3 +114,12 @@ test_sld_7: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 100 + +test_sld_7_constant: + li r4, -1 + li r5, 100 + sld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 diff --git a/src/xenia/cpu/frontend/test/instr_slw.s b/src/xenia/cpu/frontend/test/instr_slw.s index 98438a18b..b1f4af3d1 100644 --- a/src/xenia/cpu/frontend/test/instr_slw.s +++ b/src/xenia/cpu/frontend/test/instr_slw.s @@ -7,6 +7,15 @@ test_slw_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0 +test_slw_1_constant: + li r4, 1 + li r5, 0 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + test_slw_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -16,6 +25,15 @@ test_slw_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0 +test_slw_2_constant: + li r4, -1 + li r5, 0 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + test_slw_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -25,6 +43,15 @@ test_slw_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_slw_3_constant: + li r4, -1 + li r5, 1 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_slw_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -34,6 +61,15 @@ test_slw_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 63 +test_slw_4_constant: + li r4, -1 + li r5, 63 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + test_slw_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -43,6 +79,15 @@ test_slw_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 64 +test_slw_5_constant: + li r4, -1 + li r5, 64 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + test_slw_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -52,6 +97,15 @@ test_slw_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 100 +test_slw_6_constant: + li r4, -1 + li r5, 100 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + test_slw_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 30 @@ -61,6 +115,15 @@ test_slw_7: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 30 +test_slw_7_constant: + li r4, -1 + li r5, 30 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000c0000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + test_slw_8: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 31 @@ -70,6 +133,15 @@ test_slw_8: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 31 +test_slw_8_constant: + li r4, -1 + li r5, 31 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000080000000 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + test_slw_9: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 32 @@ -78,3 +150,12 @@ test_slw_9: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 32 + +test_slw_9_constant: + li r4, -1 + li r5, 32 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32 diff --git a/src/xenia/cpu/frontend/test/instr_srad.s b/src/xenia/cpu/frontend/test/instr_srad.s index 9d9b400d5..9afff4a0c 100644 --- a/src/xenia/cpu/frontend/test/instr_srad.s +++ b/src/xenia/cpu/frontend/test/instr_srad.s @@ -9,6 +9,17 @@ test_srad_1: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +test_srad_1_constant: + li r4, 1 + li r5, 0 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + test_srad_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -20,6 +31,17 @@ test_srad_2: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +test_srad_2_constant: + li r4, -1 + li r5, 0 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + test_srad_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -31,6 +53,17 @@ test_srad_3: #_ REGISTER_OUT r5 1 #_ REGISTER_OUT r6 1 +test_srad_3_constant: + li r4, -1 + li r5, 1 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + test_srad_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 62 @@ -42,6 +75,17 @@ test_srad_4: #_ REGISTER_OUT r5 62 #_ REGISTER_OUT r6 1 +test_srad_4_constant: + li r4, -1 + li r5, 62 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + #_ REGISTER_OUT r6 1 + test_srad_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -53,6 +97,17 @@ test_srad_5: #_ REGISTER_OUT r5 63 #_ REGISTER_OUT r6 1 +test_srad_5_constant: + li r4, -1 + li r5, 63 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + #_ REGISTER_OUT r6 1 + test_srad_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -64,6 +119,17 @@ test_srad_6: #_ REGISTER_OUT r5 64 #_ REGISTER_OUT r6 1 +test_srad_6_constant: + li r4, -1 + li r5, 64 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + #_ REGISTER_OUT r6 1 + test_srad_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -74,3 +140,14 @@ test_srad_7: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 100 #_ REGISTER_OUT r6 1 + +test_srad_7_constant: + li r4, -1 + li r5, 100 + srad r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_sradi.s b/src/xenia/cpu/frontend/test/instr_sradi.s index 4315f22ed..20a7dd9c8 100644 --- a/src/xenia/cpu/frontend/test/instr_sradi.s +++ b/src/xenia/cpu/frontend/test/instr_sradi.s @@ -7,6 +7,15 @@ test_sradi_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 0 +test_sradi_1_constant: + li r4, 1 + sradi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + test_sradi_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF sradi r3, r4, 0 @@ -16,6 +25,15 @@ test_sradi_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 0 +test_sradi_2_constant: + li r4, -1 + sradi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + test_sradi_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF sradi r3, r4, 1 @@ -25,6 +43,15 @@ test_sradi_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_sradi_3_constant: + li r4, -1 + sradi r3, r4, 1 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_sradi_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF sradi r3, r4, 62 @@ -34,6 +61,15 @@ test_sradi_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_sradi_4_constant: + li r4, -1 + sradi r3, r4, 62 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_sradi_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF sradi r3, r4, 63 @@ -42,3 +78,12 @@ test_sradi_5: #_ REGISTER_OUT r3 0xffffffffffffffff #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 + +test_sradi_5_constant: + li r4, -1 + sradi r3, r4, 63 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_sraw.s b/src/xenia/cpu/frontend/test/instr_sraw.s index 888ff900d..8b9b803bf 100644 --- a/src/xenia/cpu/frontend/test/instr_sraw.s +++ b/src/xenia/cpu/frontend/test/instr_sraw.s @@ -9,6 +9,17 @@ test_sraw_1: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +test_sraw_1_constant: + li r4, 1 + li r5, 0 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + test_sraw_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -20,6 +31,17 @@ test_sraw_2: #_ REGISTER_OUT r5 0 #_ REGISTER_OUT r6 0 +test_sraw_2_constant: + li r4, -1 + li r5, 0 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + test_sraw_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -31,6 +53,17 @@ test_sraw_3: #_ REGISTER_OUT r5 1 #_ REGISTER_OUT r6 1 +test_sraw_3_constant: + li r4, -1 + li r5, 1 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + test_sraw_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -42,6 +75,17 @@ test_sraw_4: #_ REGISTER_OUT r5 63 #_ REGISTER_OUT r6 1 +test_sraw_4_constant: + li r4, -1 + li r5, 63 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + #_ REGISTER_OUT r6 1 + test_sraw_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -53,6 +97,17 @@ test_sraw_5: #_ REGISTER_OUT r5 64 #_ REGISTER_OUT r6 0 +test_sraw_5_constant: + li r4, -1 + li r5, 64 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + #_ REGISTER_OUT r6 0 + test_sraw_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -64,6 +119,17 @@ test_sraw_6: #_ REGISTER_OUT r5 100 #_ REGISTER_OUT r6 1 +test_sraw_6_constant: + li r4, -1 + li r5, 100 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100 + #_ REGISTER_OUT r6 1 + test_sraw_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 30 @@ -75,6 +141,17 @@ test_sraw_7: #_ REGISTER_OUT r5 30 #_ REGISTER_OUT r6 1 +test_sraw_7_constant: + li r4, -1 + li r5, 30 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 30 + #_ REGISTER_OUT r6 1 + test_sraw_8: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 31 @@ -86,6 +163,17 @@ test_sraw_8: #_ REGISTER_OUT r5 31 #_ REGISTER_OUT r6 1 +test_sraw_8_constant: + li r4, -1 + li r5, 31 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 31 + #_ REGISTER_OUT r6 1 + test_sraw_9: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 32 @@ -96,3 +184,14 @@ test_sraw_9: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 32 #_ REGISTER_OUT r6 1 + +test_sraw_9_constant: + li r4, -1 + li r5, 32 + sraw r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 32 + #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_srawi.s b/src/xenia/cpu/frontend/test/instr_srawi.s index 725c688d8..d1477d490 100644 --- a/src/xenia/cpu/frontend/test/instr_srawi.s +++ b/src/xenia/cpu/frontend/test/instr_srawi.s @@ -7,6 +7,15 @@ test_srawi_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r6 0 +test_srawi_1_constant: + li r4, 1 + srawi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + test_srawi_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF srawi r3, r4, 0 @@ -16,6 +25,15 @@ test_srawi_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 0 +test_srawi_2_constant: + li r4, -1 + srawi r3, r4, 0 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + test_srawi_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF srawi r3, r4, 1 @@ -25,6 +43,15 @@ test_srawi_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_srawi_3_constant: + li r4, -1 + srawi r3, r4, 1 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_srawi_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF srawi r3, r4, 30 @@ -34,6 +61,15 @@ test_srawi_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 +test_srawi_4_constant: + li r4, -1 + srawi r3, r4, 30 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + test_srawi_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF srawi r3, r4, 31 @@ -42,3 +78,12 @@ test_srawi_5: #_ REGISTER_OUT r3 0xffffffffffffffff #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r6 1 + +test_srawi_5_constant: + li r4, -1 + srawi r3, r4, 31 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xffffffffffffffff + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/xenia/cpu/frontend/test/instr_srd.s b/src/xenia/cpu/frontend/test/instr_srd.s index c6d2e0707..ca330a92e 100644 --- a/src/xenia/cpu/frontend/test/instr_srd.s +++ b/src/xenia/cpu/frontend/test/instr_srd.s @@ -7,6 +7,15 @@ test_srd_1: #_ REGISTER_OUT r4 1 #_ REGISTER_OUT r5 0 +test_srd_1_constant: + li r4, 1 + li r5, 0 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + test_srd_2: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 0 @@ -16,6 +25,15 @@ test_srd_2: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 0 +test_srd_2_constant: + li r4, -1 + li r5, 0 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + test_srd_3: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 1 @@ -25,6 +43,15 @@ test_srd_3: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 1 +test_srd_3_constant: + li r4, -1 + li r5, 1 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + test_srd_4: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 62 @@ -34,6 +61,15 @@ test_srd_4: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 62 +test_srd_4_constant: + li r4, -1 + li r5, 62 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000003 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 62 + test_srd_5: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 63 @@ -43,6 +79,15 @@ test_srd_5: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 63 +test_srd_5_constant: + li r4, -1 + li r5, 63 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 63 + test_srd_6: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 64 @@ -52,6 +97,15 @@ test_srd_6: #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 64 +test_srd_6_constant: + li r4, -1 + li r5, 64 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 64 + test_srd_7: #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_IN r5 100 @@ -60,3 +114,12 @@ test_srd_7: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 100 + +test_srd_7_constant: + li r4, -1 + li r5, 100 + srd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 100