[a64] Implement `OPCODE_UNPACK`
This is a very literal translation from the x64 code into ARM and may not be very optimized. Passes unit test save for a couple off-by-one errors.
This commit is contained in:
Wunkolo
parent
6478623d47
commit
96d444da9c
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@ -1697,17 +1697,371 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
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break;
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}
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}
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static void EmitD3DCOLOR(A64Emitter& e, const EmitArgType& i) {}
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static void EmitFLOAT16_2(A64Emitter& e, const EmitArgType& i) {}
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static void EmitFLOAT16_4(A64Emitter& e, const EmitArgType& i) {}
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static void EmitSHORT_2(A64Emitter& e, const EmitArgType& i) {}
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static void EmitSHORT_4(A64Emitter& e, const EmitArgType& i) {}
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static void EmitUINT_2101010(A64Emitter& e, const EmitArgType& i) {}
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static void EmitULONG_4202020(A64Emitter& e, const EmitArgType& i) {}
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static void EmitD3DCOLOR(A64Emitter& e, const EmitArgType& i) {
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// ARGB (WXYZ) -> RGBA (XYZW)
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QReg src(0);
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if (i.src1.is_constant) {
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if (i.src1.value->IsConstantZero()) {
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e.MOVP2R(X0, e.GetVConstPtr(VOne));
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e.LDR(i.dest.reg(), X0);
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return;
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}
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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// src = ZZYYXXWW
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// Unpack to 000000ZZ,000000YY,000000XX,000000WW
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackD3DCOLOR));
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e.LDR(Q1, X0);
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e.TBL(i.dest.reg().B16(), oaknut::List{src.B16()}, Q1.B16());
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// Add 1.0f to each.
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e.MOVP2R(X0, e.GetVConstPtr(VOne));
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e.LDR(Q1, X0);
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e.EOR(i.dest.reg().B16(), i.dest.reg().B16(), Q1.B16());
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// To convert to 0 to 1, games multiply by 0x47008081 and add 0xC7008081.
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}
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static uint8x16_t EmulateFLOAT16_2(void*, std::byte src1[16]) {
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alignas(16) uint16_t a[4];
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alignas(16) float b[8];
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vst1q_u8(a, vld1q_u8(src1));
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std::memset(b, 0, sizeof(b));
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for (int i = 0; i < 2; i++) {
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b[i] = half_float::detail::half2float(a[VEC128_W(6 + i)]);
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}
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// Constants, or something
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b[2] = 0.f;
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b[3] = 1.f;
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return vld1q_u8(b);
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}
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static void EmitFLOAT16_2(A64Emitter& e, const EmitArgType& i) {
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// 1 bit sign, 5 bit exponent, 10 bit mantissa
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// D3D10 half float format
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// TODO(wunkolo): FP16 + FCVTL
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if (i.src1.is_constant) {
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e.ADD(e.GetNativeParam(0), SP, e.StashConstantV(0, i.src1.constant()));
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} else {
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e.ADD(e.GetNativeParam(0), SP, e.StashV(0, i.src1));
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}
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e.CallNativeSafe(reinterpret_cast<void*>(EmulateFLOAT16_2));
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e.MOV(i.dest.reg().B16(), Q0.B16());
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}
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static uint8x16_t EmulateFLOAT16_4(void*, std::byte src1[16]) {
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alignas(16) uint16_t a[4];
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alignas(16) float b[8];
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vst1q_u8(a, vld1q_u8(src1));
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for (int i = 0; i < 4; i++) {
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b[i] = half_float::detail::half2float(a[VEC128_W(4 + i)]);
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}
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return vld1q_u8(b);
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}
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static void EmitFLOAT16_4(A64Emitter& e, const EmitArgType& i) {
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// src = [(dest.x | dest.y), (dest.z | dest.w), 0, 0]
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// TODO(wunkolo): FP16 + FCVTN
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if (i.src1.is_constant) {
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e.ADD(e.GetNativeParam(0), SP, e.StashConstantV(0, i.src1.constant()));
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} else {
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e.ADD(e.GetNativeParam(0), SP, e.StashV(0, i.src1));
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}
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e.CallNativeSafe(reinterpret_cast<void*>(EmulateFLOAT16_4));
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e.MOV(i.dest.reg().B16(), Q0.B16());
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}
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static void EmitSHORT_2(A64Emitter& e, const EmitArgType& i) {
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// (VD.x) = 3.0 + (VB.x>>16)*2^-22
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// (VD.y) = 3.0 + (VB.x)*2^-22
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// (VD.z) = 0.0
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// (VD.w) = 1.0 (games splat W after unpacking to get vectors of 1.0f)
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// src is (xx,xx,xx,VALUE)
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QReg src(0);
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if (i.src1.is_constant) {
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if (i.src1.value->IsConstantZero()) {
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src = i.dest;
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e.MOVP2R(X0, e.GetVConstPtr(V3301));
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e.LDR(i.dest, X0);
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return;
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}
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// TODO(benvanik): check other common constants/perform shuffle/or here.
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src = i.src1;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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// Shuffle bytes.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackSHORT_2));
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e.LDR(Q1, X0);
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e.TBL(i.dest.reg().B16(), oaknut::List{src.B16()}, Q1.B16());
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// If negative, make smaller than 3 - sign extend before adding.
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e.SHL(i.dest.reg().S4(), i.dest.reg().S4(), 16);
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e.SSHR(i.dest.reg().S4(), i.dest.reg().S4(), 16);
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// Add 3,3,0,1.
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e.MOVP2R(X0, e.GetVConstPtr(V3301));
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e.LDR(Q1, X0);
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e.ADD(i.dest.reg().S4(), i.dest.reg().S4(), Q1.S4());
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// Return quiet NaNs in case of negative overflow.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackSHORT_Overflow));
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e.LDR(Q1, X0);
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e.CMEQ(Q0.S4(), i.dest.reg().S4(), Q1.S4());
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e.MOVP2R(X0, e.GetVConstPtr(VQNaN));
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e.LDR(Q1, X0);
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e.BSL(Q0.B16(), Q1.B16(), i.dest.reg().B16());
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e.MOV(i.dest.reg().B16(), Q0.B16());
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}
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static void EmitSHORT_4(A64Emitter& e, const EmitArgType& i) {
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// (VD.x) = 3.0 + (VB.x>>16)*2^-22
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// (VD.y) = 3.0 + (VB.x)*2^-22
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// (VD.z) = 3.0 + (VB.y>>16)*2^-22
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// (VD.w) = 3.0 + (VB.y)*2^-22
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// src is (xx,xx,VALUE,VALUE)
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QReg src(0);
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if (i.src1.is_constant) {
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if (i.src1.value->IsConstantZero()) {
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e.MOVP2R(X0, e.GetVConstPtr(V3333));
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e.LDR(i.dest, X0);
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return;
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}
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// TODO(benvanik): check other common constants/perform shuffle/or here.
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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// Shuffle bytes.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackSHORT_4));
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e.LDR(Q1, X0);
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e.TBL(i.dest.reg().B16(), oaknut::List{src.B16()}, Q1.B16());
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// If negative, make smaller than 3 - sign extend before adding.
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e.SHL(i.dest.reg().S4(), i.dest.reg().S4(), 16);
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e.SSHR(i.dest.reg().S4(), i.dest.reg().S4(), 16);
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// Add 3,3,3,3.
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e.MOVP2R(X0, e.GetVConstPtr(V3333));
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e.LDR(Q1, X0);
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e.ADD(i.dest.reg().S4(), i.dest.reg().S4(), Q1.S4());
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// Return quiet NaNs in case of negative overflow.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackSHORT_Overflow));
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e.LDR(Q1, X0);
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e.CMEQ(Q0.S4(), i.dest.reg().S4(), Q1.S4());
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e.MOVP2R(X0, e.GetVConstPtr(VQNaN));
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e.LDR(Q1, X0);
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e.BSL(Q0.B16(), Q1.B16(), i.dest.reg().B16());
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e.MOV(i.dest.reg().B16(), Q0.B16());
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}
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static void EmitUINT_2101010(A64Emitter& e, const EmitArgType& i) {
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QReg src(0);
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if (i.src1.is_constant) {
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if (i.src1.value->IsConstantZero()) {
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e.MOVP2R(X0, e.GetVConstPtr(V3331));
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e.LDR(i.dest, X0);
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return;
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}
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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// Splat W.
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e.DUP(i.dest.reg().S4(), src.Selem()[3]);
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// Keep only the needed components.
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// Red in 0-9 now, green in 10-19, blue in 20-29, alpha in 30-31.
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e.MOVP2R(X0, e.GetVConstPtr(VPackUINT_2101010_MaskPacked));
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e.LDR(Q1, X0);
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e.AND(i.dest.reg().B16(), i.dest.reg().B16(), Q1.B16());
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// Shift the components down.
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e.MOVP2R(X0, e.GetVConstPtr(VPackUINT_2101010_Shift));
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e.LDR(Q1, X0);
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e.NEG(Q1.S4(), Q1.S4());
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e.USHL(i.dest.reg().S4(), i.dest.reg().S4(), Q1.S4());
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// If XYZ are negative, make smaller than 3 - sign extend XYZ before adding.
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// W is unsigned.
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e.SHL(i.dest.reg().S4(), i.dest.reg().S4(), 22);
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e.SSHR(i.dest.reg().S4(), i.dest.reg().S4(), 22);
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// Add 3,3,3,1.
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e.MOVP2R(X0, e.GetVConstPtr(V3331));
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e.LDR(Q1, X0);
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e.ADD(i.dest.reg().S4(), i.dest.reg().S4(), Q1.S4());
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// Return quiet NaNs in case of negative overflow.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackUINT_2101010_Overflow));
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e.LDR(Q1, X0);
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e.CMEQ(Q0.S4(), i.dest.reg().S4(), Q1.S4());
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e.MOVP2R(X0, e.GetVConstPtr(VQNaN));
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e.LDR(Q1, X0);
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e.BSL(Q0.B16(), Q1.B16(), i.dest.reg().B16());
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e.MOV(i.dest.reg().B16(), Q0.B16());
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// To convert XYZ to -1 to 1, games multiply by 0x46004020 & sub 0x46C06030.
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// For W to 0 to 1, they multiply by and subtract 0x4A2AAAAB.}
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}
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static void EmitULONG_4202020(A64Emitter& e, const EmitArgType& i) {
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QReg src(0);
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if (i.src1.is_constant) {
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if (i.src1.value->IsConstantZero()) {
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e.MOVP2R(X0, e.GetVConstPtr(V3331));
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e.LDR(i.dest, X0);
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return;
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}
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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// Extract pairs of nibbles to XZYW. XZ will have excess 4 upper bits, YW
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// will have excess 4 lower bits.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackULONG_4202020_Permute));
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e.LDR(Q1, X0);
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e.TBL(i.dest.reg().B16(), oaknut::List{src.B16()}, Q1.B16());
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// Drop the excess nibble of YW.
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e.USHR(Q0.S4(), i.dest.reg().S4(), 4);
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// Merge XZ and YW now both starting at offset 0.
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e.LoadConstantV(Q1, vec128i(3 * 0x04'04'04'04 + 0x03'02'01'00,
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2 * 0x04'04'04'04 + 0x03'02'01'00,
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1 * 0x04'04'04'04 + 0x03'02'01'00,
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0 * 0x04'04'04'04 + 0x03'02'01'00));
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e.TBL(i.dest.reg().B16(), oaknut::List{i.dest.reg().B16(), Q0.B16()},
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Q1.B16());
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// Reorder as XYZW.
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e.LoadConstantV(Q1, vec128i(3 * 0x04'04'04'04 + 0x03'02'01'00,
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1 * 0x04'04'04'04 + 0x03'02'01'00,
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2 * 0x04'04'04'04 + 0x03'02'01'00,
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0 * 0x04'04'04'04 + 0x03'02'01'00));
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e.TBL(i.dest.reg().B16(), oaknut::List{i.dest.reg().B16(), Q0.B16()},
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Q1.B16());
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// Drop the excess upper nibble in XZ and sign-extend XYZ.
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e.SHL(i.dest.reg().S4(), i.dest.reg().S4(), 12);
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e.SSHR(i.dest.reg().S4(), i.dest.reg().S4(), 12);
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// Add 3,3,3,1.
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e.MOVP2R(X0, e.GetVConstPtr(V3331));
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e.LDR(Q1, X0);
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e.ADD(i.dest.reg().S4(), i.dest.reg().S4(), Q1.S4());
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// Return quiet NaNs in case of negative overflow.
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e.MOVP2R(X0, e.GetVConstPtr(VUnpackULONG_4202020_Overflow));
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e.LDR(Q1, X0);
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e.CMEQ(Q0.S4(), i.dest.reg().S4(), Q1.S4());
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e.MOVP2R(X0, e.GetVConstPtr(VQNaN));
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e.LDR(Q1, X0);
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e.BSL(Q0.B16(), Q1.B16(), i.dest.reg().B16());
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e.MOV(i.dest.reg().B16(), Q0.B16());
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}
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static void Emit8_IN_16(A64Emitter& e, const EmitArgType& i, uint32_t flags) {
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assert_false(IsPackOutSaturate(flags));
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QReg src(0);
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if (i.src1.is_constant) {
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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if (IsPackToLo(flags)) {
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// Unpack to LO.
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if (IsPackInUnsigned(flags)) {
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if (IsPackOutUnsigned(flags)) {
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// unsigned -> unsigned
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assert_always();
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} else {
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// unsigned -> signed
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assert_always();
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}
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} else {
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if (IsPackOutUnsigned(flags)) {
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// signed -> unsigned
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assert_always();
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} else {
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// signed -> signed
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e.REV32(i.dest.reg().H8(), i.dest.reg().H8());
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e.SXTL2(i.dest.reg().H8(), i.dest.reg().B16());
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}
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}
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} else {
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// Unpack to HI.
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if (IsPackInUnsigned(flags)) {
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if (IsPackOutUnsigned(flags)) {
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// unsigned -> unsigned
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assert_always();
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} else {
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// unsigned -> signed
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assert_always();
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}
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} else {
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if (IsPackOutUnsigned(flags)) {
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// signed -> unsigned
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assert_always();
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} else {
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// signed -> signed
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e.REV32(i.dest.reg().H8(), i.dest.reg().H8());
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e.SXTL(i.dest.reg().H8(), i.dest.reg().toD().B8());
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}
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}
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}
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}
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static void Emit16_IN_32(A64Emitter& e, const EmitArgType& i,
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uint32_t flags) {}
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uint32_t flags) {
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assert_false(IsPackOutSaturate(flags));
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QReg src(0);
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if (i.src1.is_constant) {
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src = i.dest;
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e.LoadConstantV(src, i.src1.constant());
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} else {
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src = i.src1;
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}
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if (IsPackToLo(flags)) {
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// Unpack to LO.
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if (IsPackInUnsigned(flags)) {
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if (IsPackOutUnsigned(flags)) {
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// unsigned -> unsigned
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assert_always();
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} else {
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// unsigned -> signed
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assert_always();
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}
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} else {
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if (IsPackOutUnsigned(flags)) {
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// signed -> unsigned
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assert_always();
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} else {
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// signed -> signed
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e.SXTL2(i.dest.reg().S4(), src.H8());
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}
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}
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} else {
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// Unpack to HI.
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if (IsPackInUnsigned(flags)) {
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if (IsPackOutUnsigned(flags)) {
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// unsigned -> unsigned
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assert_always();
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} else {
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// unsigned -> signed
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assert_always();
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}
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} else {
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if (IsPackOutUnsigned(flags)) {
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// signed -> unsigned
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assert_always();
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} else {
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// signed -> signed
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e.SXTL(i.dest.reg().S4(), src.toD().H4());
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}
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}
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}
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e.REV64(i.dest.reg().S4(), i.dest.reg().S4());
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}
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};
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EMITTER_OPCODE_TABLE(OPCODE_UNPACK, UNPACK);
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