From 952819ed87c29a81f55db1eca87bb20e187c95e7 Mon Sep 17 00:00:00 2001 From: Triang3l Date: Thu, 13 Dec 2018 15:22:16 +0300 Subject: [PATCH] [D3D12] Don't 4KB-align sizes of resolve destinations --- src/xenia/gpu/d3d12/render_target_cache.cc | 2 +- src/xenia/gpu/d3d12/texture_cache.cc | 2 +- src/xenia/gpu/texture_util.cc | 8 ++++++-- src/xenia/gpu/texture_util.h | 6 ++++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/xenia/gpu/d3d12/render_target_cache.cc b/src/xenia/gpu/d3d12/render_target_cache.cc index 63cb4b49f..25bc86cd5 100644 --- a/src/xenia/gpu/d3d12/render_target_cache.cc +++ b/src/xenia/gpu/d3d12/render_target_cache.cc @@ -1208,7 +1208,7 @@ bool RenderTargetCache::ResolveCopy(SharedMemory* shared_memory, uint32_t dest_size = texture_util::GetGuestMipSliceStorageSize( xe::align(dest_pitch, 32u), xe::align(uint32_t(rect.bottom - (rect.top & ~LONG(31))), 32u), 1, true, - dest_format, nullptr); + dest_format, nullptr, false); uint32_t dest_offset_x = uint32_t(rect.left) & 31; uint32_t dest_offset_y = uint32_t(rect.top) & 31; // Make sure we have the memory to write to. diff --git a/src/xenia/gpu/d3d12/texture_cache.cc b/src/xenia/gpu/d3d12/texture_cache.cc index 928f0ecb1..7c8dc7087 100644 --- a/src/xenia/gpu/d3d12/texture_cache.cc +++ b/src/xenia/gpu/d3d12/texture_cache.cc @@ -1091,7 +1091,7 @@ bool TextureCache::TileResolvedTexture( offset_y &= 31; uint32_t texture_size = texture_util::GetGuestMipSliceStorageSize( texture_pitch, xe::align(offset_y + resolve_height, 32u), 1, true, format, - nullptr); + nullptr, false); if (texture_size == 0) { return true; } diff --git a/src/xenia/gpu/texture_util.cc b/src/xenia/gpu/texture_util.cc index f46f1655d..c3c8f3502 100644 --- a/src/xenia/gpu/texture_util.cc +++ b/src/xenia/gpu/texture_util.cc @@ -58,7 +58,7 @@ uint32_t GetGuestMipSliceStorageSize(uint32_t width_blocks, uint32_t height_blocks, uint32_t depth_blocks, bool is_tiled, TextureFormat format, - uint32_t* row_pitch_out) { + uint32_t* row_pitch_out, bool align_4kb) { const FormatInfo* format_info = FormatInfo::Get(format); uint32_t row_pitch = width_blocks * format_info->block_width * format_info->block_height * format_info->bits_per_pixel / @@ -69,7 +69,11 @@ uint32_t GetGuestMipSliceStorageSize(uint32_t width_blocks, if (row_pitch_out != nullptr) { *row_pitch_out = row_pitch; } - return xe::align(row_pitch * height_blocks * depth_blocks, 4096u); + uint32_t size = row_pitch * height_blocks * depth_blocks; + if (align_4kb) { + size = xe::align(size, 4096u); + } + return size; } bool GetPackedMipOffset(uint32_t width, uint32_t height, uint32_t depth, diff --git a/src/xenia/gpu/texture_util.h b/src/xenia/gpu/texture_util.h index c30d4a149..e762eb961 100644 --- a/src/xenia/gpu/texture_util.h +++ b/src/xenia/gpu/texture_util.h @@ -31,12 +31,14 @@ void GetGuestMipBlocks(Dimension dimension, uint32_t width, uint32_t height, // Calculates the number of bytes required to store a single array slice within // a single mip level - width, height and depth must be obtained via -// GetGuestMipBlocks. +// GetGuestMipBlocks. align_4kb can be set to false when calculating relatively +// to some offset in the texture rather than the top-left corner of it. uint32_t GetGuestMipSliceStorageSize(uint32_t width_blocks, uint32_t height_blocks, uint32_t depth_blocks, bool is_tiled, TextureFormat format, - uint32_t* row_pitch_out); + uint32_t* row_pitch_out, + bool align_4kb = true); // Gets the number of the mipmap level where the packed mips are stored. inline uint32_t GetPackedMipLevel(uint32_t width, uint32_t height) {