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Test vupkd3d128 and fix short2 unpacking.

This commit is contained in:
Ben Vanik 2015-01-19 11:46:14 -08:00
parent 1d4ee3e6fb
commit 9099f597fe
5 changed files with 87 additions and 1 deletions
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5
src/alloy/backend/x64/x64_sequences.cc
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@ -5364,8 +5364,11 @@ EMITTER(UNPACK, MATCH(I<OPCODE_UNPACK, V128<>, V128<>>)) {
}
// Shuffle bytes.
e.vpshufb(i.dest, src, e.GetXmmConstPtr(XMMUnpackSHORT_2));
// Sign extend words.
e.vpslld(i.dest, 16);
e.vpsrad(i.dest, 16);
// Add 3,3,0,1.
e.vpor(i.dest, e.GetXmmConstPtr(XMM3301));
e.vpaddd(i.dest, e.GetXmmConstPtr(XMM3301));
}
static void Emit8_IN_16(X64Emitter& e, const EmitArgType& i, uint32_t flags) {
assert_false(IsPackOutSaturate(flags));

BIN
src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.bin Normal file
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29
src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.dis Normal file
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@ -0,0 +1,29 @@
/vagrant/src/alloy/frontend/ppc/test/bin//instr_vupkd3d128.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_vupkd3d128_d3dcolor>:
100000: 18 60 1f f0 vupkd3d128 v3,v3,0
100004: 4e 80 00 20 blr
0000000000100008 <test_vupkd3d128_short2_0>:
100008: 18 64 1f f0 vupkd3d128 v3,v3,4
10000c: 4e 80 00 20 blr
0000000000100010 <test_vupkd3d128_short2_1>:
100010: 18 64 1f f0 vupkd3d128 v3,v3,4
100014: 4e 80 00 20 blr
0000000000100018 <test_vupkd3d128_short2_2>:
100018: 18 64 1f f0 vupkd3d128 v3,v3,4
10001c: 4e 80 00 20 blr
0000000000100020 <test_vupkd3d128_float16_2_0>:
100020: 18 6c 1f f0 vupkd3d128 v3,v3,12
100024: 4e 80 00 20 blr
0000000000100028 <test_vupkd3d128_float16_4_0>:
100028: 18 74 1f f0 vupkd3d128 v3,v3,20
10002c: 4e 80 00 20 blr

6
src/alloy/frontend/ppc/test/bin/instr_vupkd3d128.map Normal file
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@ -0,0 +1,6 @@
0000000000000000 t test_vupkd3d128_d3dcolor
0000000000000008 t test_vupkd3d128_short2_0
0000000000000010 t test_vupkd3d128_short2_1
0000000000000018 t test_vupkd3d128_short2_2
0000000000000020 t test_vupkd3d128_float16_2_0
0000000000000028 t test_vupkd3d128_float16_4_0

48
src/alloy/frontend/ppc/test/instr_vupkd3d128.s Normal file
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@ -0,0 +1,48 @@
# vupkd3d128 dest, src, type
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 3 = PACK_TYPE_FLOAT16_2
# 5 = PACK_TYPE_FLOAT16_4
# vupkd3d128 is broken in binutils, so these are hand coded
test_vupkd3d128_d3dcolor:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
# vupkd3d128 v3, v3, 0
.long 0x18601FF0
blr
#_ REGISTER_OUT v3 [3f800001, 3f800002, 3f800003, 3f800004]
test_vupkd3d128_short2_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40407fff, 403f8001, 00000000, 3f800000]
test_vupkd3d128_short2_1:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40404000, 403FC000, 00000000, 3f800000]
test_vupkd3d128_short2_2:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40407FFF, 403FF333, 00000000, 3f800000]
test_vupkd3d128_float16_2_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
# vupkd3d128 v3, v3, 3
.long 0x186C1FF0
blr
#_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 3f800000]
test_vupkd3d128_float16_4_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 3800B801, 3802B803]
# vupkd3d128 v3, v3, 5
.long 0x18741FF0
blr
#_ REGISTER_OUT v3 [3F000000, bf002000, 3f004000, bf006000]