diff --git a/src/xenia/gpu/register_table.inc b/src/xenia/gpu/register_table.inc
index 18ad64a0f..856b7c832 100644
--- a/src/xenia/gpu/register_table.inc
+++ b/src/xenia/gpu/register_table.inc
@@ -49,6 +49,22 @@ XE_GPU_REGISTER(0x0E42, kDword, UNKNOWN_0E42)
 
 XE_GPU_REGISTER(0x0F01, kDword, RB_BC_CONTROL)
 
+// D1*, LUT, and AVIVO registers taken from libxenon and https://www.x.org/docs/AMD/old/RRG-216M56-03oOEM.pdf
+XE_GPU_REGISTER(0x1838, kDword, D1MODE_MASTER_UPDATE_LOCK)
+
+XE_GPU_REGISTER(0x1841, kDword, D1GRPH_CONTROL)
+XE_GPU_REGISTER(0x1844, kDword, D1GRPH_PRIMARY_SURFACE_ADDRESS)
+XE_GPU_REGISTER(0x1852, kDword, D1GRPH_FLIP_CONTROL)
+
+XE_GPU_REGISTER(0x1921, kDword, DC_LUT_RW_MODE)
+XE_GPU_REGISTER(0x1922, kDword, DC_LUT_RW_INDEX)
+XE_GPU_REGISTER(0x1925, kDword, DC_LUT_30_COLOR)
+XE_GPU_REGISTER(0x1927, kDword, DC_LUT_WRITE_EN_MASK)
+XE_GPU_REGISTER(0x1930, kDword, DC_LUTA_CONTROL)
+
+XE_GPU_REGISTER(0x1964, kDword, AVIVO_D1SCL_SCALER_ENABLE)
+XE_GPU_REGISTER(0x1973, kDword, AVIVO_D1SCL_UPDATE)
+
 XE_GPU_REGISTER(0x2000, kDword, RB_SURFACE_INFO)
 XE_GPU_REGISTER(0x2001, kDword, RB_COLOR_INFO)
 XE_GPU_REGISTER(0x2002, kDword, RB_DEPTH_INFO)