[GPU] Make some gaps in the register table more obvious.
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@ -43,6 +43,7 @@ XE_GPU_REGISTER(0x0A31, kDword, COHER_STATUS_HOST)
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XE_GPU_REGISTER(0x0D00, kDword, SQ_GPR_MANAGEMENT)
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XE_GPU_REGISTER(0x0D01, kDword, SQ_FLOW_CONTROL)
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XE_GPU_REGISTER(0x0D02, kDword, SQ_INST_STORE_MANAGMENT)
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XE_GPU_REGISTER(0x0D04, kDword, SQ_EO_RT)
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XE_GPU_REGISTER(0x0C85, kDword, PA_CL_ENHANCE)
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@ -60,18 +61,25 @@ XE_GPU_REGISTER(0x0F02, kDword, RB_EDRAM_INFO)
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XE_GPU_REGISTER(0x1838, kDword, D1MODE_MASTER_UPDATE_LOCK)
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XE_GPU_REGISTER(0x1841, kDword, D1GRPH_CONTROL)
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XE_GPU_REGISTER(0x1844, kDword, D1GRPH_PRIMARY_SURFACE_ADDRESS)
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XE_GPU_REGISTER(0x1852, kDword, D1GRPH_FLIP_CONTROL)
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XE_GPU_REGISTER(0x1921, kDword, DC_LUT_RW_MODE)
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XE_GPU_REGISTER(0x1922, kDword, DC_LUT_RW_INDEX)
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XE_GPU_REGISTER(0x1924, kDword, DC_LUT_PWL_DATA)
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XE_GPU_REGISTER(0x1925, kDword, DC_LUT_30_COLOR)
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XE_GPU_REGISTER(0x1927, kDword, DC_LUT_WRITE_EN_MASK)
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XE_GPU_REGISTER(0x1930, kDword, DC_LUTA_CONTROL)
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XE_GPU_REGISTER(0x1961, kDword, AVIVO_D1MODE_VIEWPORT_SIZE)
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XE_GPU_REGISTER(0x1964, kDword, AVIVO_D1SCL_SCALER_ENABLE)
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XE_GPU_REGISTER(0x1973, kDword, AVIVO_D1SCL_UPDATE)
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XE_GPU_REGISTER(0x2000, kDword, RB_SURFACE_INFO)
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