diff --git a/src/xenia/cpu/backend/a64/a64_seq_memory.cc b/src/xenia/cpu/backend/a64/a64_seq_memory.cc
index 28bd3c414..671470eba 100644
--- a/src/xenia/cpu/backend/a64/a64_seq_memory.cc
+++ b/src/xenia/cpu/backend/a64/a64_seq_memory.cc
@@ -1101,7 +1101,11 @@ EMITTER_OPCODE_TABLE(OPCODE_CACHE_CONTROL, CACHE_CONTROL);
 struct MEMORY_BARRIER
     : Sequence<MEMORY_BARRIER, I<OPCODE_MEMORY_BARRIER, VoidOp>> {
   static void Emit(A64Emitter& e, const EmitArgType& i) {
+    // mfence on x64 flushes all writes before any later instructions
     // e.mfence();
+
+    // This is equivalent to DMB SY
+    e.DMB(BarrierOp::SY);
   }
 };
 EMITTER_OPCODE_TABLE(OPCODE_MEMORY_BARRIER, MEMORY_BARRIER);