[a64] Fix `PERMUTE_V128` out-of-index case
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@ -1139,26 +1139,33 @@ struct PERMUTE_V128
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}
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// Indices must be endian-swapped
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e.MOVP2R(X0, e.GetVConstPtr(VSwapWordMask));
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e.LDR(Q1, X0);
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e.EOR(Q0.B16(), Q0.B16(), Q1.B16());
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e.MOV(W0, 0b11);
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e.DUP(Q1.B16(), W0);
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e.EOR(indices.B16(), indices.B16(), Q1.B16());
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// Modulo 32 the indices
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e.MOV(W0, 0b0001'1111);
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e.DUP(Q1.B16(), W0);
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e.AND(indices.B16(), indices.B16(), Q1.B16());
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// Table-registers must be sequential indices
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const QReg table0 = Q2;
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const QReg table_lo = Q2;
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if (i.src2.is_constant) {
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e.LoadConstantV(table0, i.src2.constant());
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e.LoadConstantV(table_lo, i.src2.constant());
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} else {
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e.MOV(table0.B16(), i.src2.reg().B16());
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e.MOV(table_lo.B16(), i.src2.reg().B16());
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}
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const QReg table1 = Q3;
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const QReg table_hi = Q3;
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if (i.src3.is_constant) {
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e.LoadConstantV(table1, i.src3.constant());
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e.LoadConstantV(table_hi, i.src3.constant());
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} else {
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e.MOV(table1.B16(), i.src3.reg().B16());
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e.MOV(table_hi.B16(), i.src3.reg().B16());
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}
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e.TBL(i.dest.reg().B16(), List{table0.B16(), table1.B16()}, indices.B16());
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e.TBL(i.dest.reg().B16(), List{table_lo.B16(), table_hi.B16()},
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indices.B16());
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}
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static void EmitByInt16(A64Emitter& e, const EmitArgType& i) {}
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