div tests + fix.

src/alloy/backend/ivm/ivm_intcode.cc

@@ -2989,27 +2989,33 @@ int Translate_MUL_HI(TranslationContext& ctx, Instr* i) {
 }
 
 uint32_t IntCode_DIV_I8_I8(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i8 = ics.rf[i->src1_reg].i8 / ics.rf[i->src2_reg].i8;
+  auto divisor = ics.rf[i->src2_reg].i8;
+  ics.rf[i->dest_reg].i8 = divisor ? ics.rf[i->src1_reg].i8 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I16_I16(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i16 = ics.rf[i->src1_reg].i16 / ics.rf[i->src2_reg].i16;
+  auto divisor = ics.rf[i->src2_reg].i16;
+  ics.rf[i->dest_reg].i16 = divisor ? ics.rf[i->src1_reg].i16 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I32_I32(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i32 = ics.rf[i->src1_reg].i32 / ics.rf[i->src2_reg].i32;
+  auto divisor = ics.rf[i->src2_reg].i32;
+  ics.rf[i->dest_reg].i32 = divisor ? ics.rf[i->src1_reg].i32 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I64_I64(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i64 = ics.rf[i->src1_reg].i64 / ics.rf[i->src2_reg].i64;
+  auto divisor = ics.rf[i->src2_reg].i64;
+  ics.rf[i->dest_reg].i64 = divisor ? ics.rf[i->src1_reg].i64 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_F32_F32(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].f32 = ics.rf[i->src1_reg].f32 / ics.rf[i->src2_reg].f32;
+  auto divisor = ics.rf[i->src2_reg].f32;
+  ics.rf[i->dest_reg].f32 = divisor ? ics.rf[i->src1_reg].f32 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_F64_F64(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].f64 = ics.rf[i->src1_reg].f64 / ics.rf[i->src2_reg].f64;
+  auto divisor = ics.rf[i->src2_reg].f64;
+  ics.rf[i->dest_reg].f64 = divisor ? ics.rf[i->src1_reg].f64 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_V128_V128(IntCodeState& ics, const IntCode* i) {
@@ -3022,19 +3028,23 @@ uint32_t IntCode_DIV_V128_V128(IntCodeState& ics, const IntCode* i) {
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I8_I8_U(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].u8 = ics.rf[i->src1_reg].u8 / ics.rf[i->src2_reg].u8;
+  auto divisor = ics.rf[i->src2_reg].u8;
+  ics.rf[i->dest_reg].u8 = divisor ? ics.rf[i->src1_reg].u8 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I16_I16_U(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].u16 = ics.rf[i->src1_reg].u16 / ics.rf[i->src2_reg].u16;
+  auto divisor = ics.rf[i->src2_reg].u16;
+  ics.rf[i->dest_reg].u16 = divisor ? ics.rf[i->src1_reg].u16 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I32_I32_U(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].u32 = ics.rf[i->src1_reg].u32 / ics.rf[i->src2_reg].u32;
+  auto divisor = ics.rf[i->src2_reg].u32;
+  ics.rf[i->dest_reg].u32 = divisor ? ics.rf[i->src1_reg].u32 / divisor : 0;
   return IA_NEXT;
 }
 uint32_t IntCode_DIV_I64_I64_U(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].u64 = ics.rf[i->src1_reg].u64 / ics.rf[i->src2_reg].u64;
+  auto divisor = ics.rf[i->src2_reg].u64;
+  ics.rf[i->dest_reg].u64 = divisor ? ics.rf[i->src1_reg].u64 / divisor : 0;
   return IA_NEXT;
 }
 int Translate_DIV(TranslationContext& ctx, Instr* i) {

src/alloy/frontend/ppc/ppc_emit_alu.cc

@@ -226,7 +226,7 @@ XEEMITTER(divwx, 0x7C0003D6, XO)(PPCHIRBuilder& f, InstrData& i) {
   //                 if OE=1, set XER[OV] = 1
   //                 else skip the divide
   Value* v = f.Div(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), divisor);
-  v = f.SignExtend(v, INT64_TYPE);
+  v = f.ZeroExtend(v, INT64_TYPE);
   f.StoreGPR(i.XO.RT, v);
   if (i.XO.OE) {
     // If we are OE=1 we need to clear the overflow bit.

src/alloy/frontend/ppc/test/bin/instr_divd.dis

@@ -0,0 +1,33 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_divd.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divd_1>:
+  100000:	7c 64 2b d2 	divd    r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divd_3>:
+  100008:	7c 64 2b d2 	divd    r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divd_4>:
+  100010:	7c 64 2b d2 	divd    r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divd_5>:
+  100018:	7c 64 2b d2 	divd    r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divd_6>:
+  100020:	7c 64 2b d2 	divd    r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divd_7>:
+  100028:	7c 64 2b d2 	divd    r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divd_8>:
+  100030:	7c 64 2b d2 	divd    r3,r4,r5
+  100034:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_divd.map

@@ -0,0 +1,7 @@
+0000000000000000 t test_divd_1
+0000000000000008 t test_divd_3
+0000000000000010 t test_divd_4
+0000000000000018 t test_divd_5
+0000000000000020 t test_divd_6
+0000000000000028 t test_divd_7
+0000000000000030 t test_divd_8

src/alloy/frontend/ppc/test/bin/instr_divdu.dis

@@ -0,0 +1,37 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_divdu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divdu_1>:
+  100000:	7c 64 2b 92 	divdu   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divdu_3>:
+  100008:	7c 64 2b 92 	divdu   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divdu_4>:
+  100010:	7c 64 2b 92 	divdu   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divdu_5>:
+  100018:	7c 64 2b 92 	divdu   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divdu_6>:
+  100020:	7c 64 2b 92 	divdu   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divdu_7>:
+  100028:	7c 64 2b 92 	divdu   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divdu_8>:
+  100030:	7c 64 2b 92 	divdu   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divdu_9>:
+  100038:	7c 64 2b 92 	divdu   r3,r4,r5
+  10003c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_divdu.map

@@ -0,0 +1,8 @@
+0000000000000000 t test_divdu_1
+0000000000000008 t test_divdu_3
+0000000000000010 t test_divdu_4
+0000000000000018 t test_divdu_5
+0000000000000020 t test_divdu_6
+0000000000000028 t test_divdu_7
+0000000000000030 t test_divdu_8
+0000000000000038 t test_divdu_9

src/alloy/frontend/ppc/test/bin/instr_divw.dis

@@ -0,0 +1,45 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_divw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divw_1>:
+  100000:	7c 64 2b d6 	divw    r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divw_3>:
+  100008:	7c 64 2b d6 	divw    r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divw_4>:
+  100010:	7c 64 2b d6 	divw    r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divw_5>:
+  100018:	7c 64 2b d6 	divw    r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divw_6>:
+  100020:	7c 64 2b d6 	divw    r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divw_7>:
+  100028:	7c 64 2b d6 	divw    r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divw_8>:
+  100030:	7c 64 2b d6 	divw    r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divw_9>:
+  100038:	7c 64 2b d6 	divw    r3,r4,r5
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_divw_10>:
+  100040:	7c 64 2b d6 	divw    r3,r4,r5
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_divw_11>:
+  100048:	7c 64 2b d6 	divw    r3,r4,r5
+  10004c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_divw.map

@@ -0,0 +1,10 @@
+0000000000000000 t test_divw_1
+0000000000000008 t test_divw_3
+0000000000000010 t test_divw_4
+0000000000000018 t test_divw_5
+0000000000000020 t test_divw_6
+0000000000000028 t test_divw_7
+0000000000000030 t test_divw_8
+0000000000000038 t test_divw_9
+0000000000000040 t test_divw_10
+0000000000000048 t test_divw_11

src/alloy/frontend/ppc/test/bin/instr_divwu.dis

@@ -0,0 +1,49 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_divwu.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_divwu_1>:
+  100000:	7c 64 2b 96 	divwu   r3,r4,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_divwu_3>:
+  100008:	7c 64 2b 96 	divwu   r3,r4,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_divwu_4>:
+  100010:	7c 64 2b 96 	divwu   r3,r4,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_divwu_5>:
+  100018:	7c 64 2b 96 	divwu   r3,r4,r5
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_divwu_6>:
+  100020:	7c 64 2b 96 	divwu   r3,r4,r5
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_divwu_7>:
+  100028:	7c 64 2b 96 	divwu   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_divwu_8>:
+  100030:	7c 64 2b 96 	divwu   r3,r4,r5
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_divwu_9>:
+  100038:	7c 64 2b 96 	divwu   r3,r4,r5
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_divwu_10>:
+  100040:	7c 64 2b 96 	divwu   r3,r4,r5
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_divwu_11>:
+  100048:	7c 64 2b 96 	divwu   r3,r4,r5
+  10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_divwu_12>:
+  100050:	7c 64 2b 96 	divwu   r3,r4,r5
+  100054:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_divwu.map

@@ -0,0 +1,11 @@
+0000000000000000 t test_divwu_1
+0000000000000008 t test_divwu_3
+0000000000000010 t test_divwu_4
+0000000000000018 t test_divwu_5
+0000000000000020 t test_divwu_6
+0000000000000028 t test_divwu_7
+0000000000000030 t test_divwu_8
+0000000000000038 t test_divwu_9
+0000000000000040 t test_divwu_10
+0000000000000048 t test_divwu_11
+0000000000000050 t test_divwu_12

src/alloy/frontend/ppc/test/instr_divd.s

@@ -0,0 +1,82 @@
+test_divd_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divd_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divd_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divd_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divd_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divd_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divd_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divd_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divd r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+# TODO(benvanik): integer overflow (=0)
+#test_divd_9:
+#  #_ REGISTER_IN r4 0x8000000000000000
+#  #_ REGISTER_IN r5 -1
+#  divd r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x8000000000000000
+#  #_ REGISTER_OUT r5 -1

src/alloy/frontend/ppc/test/instr_divdu.s

@@ -0,0 +1,81 @@
+test_divdu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divdu_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divdu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divdu_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divdu_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divdu_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divdu_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divdu_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divdu_9:
+  #_ REGISTER_IN r4 0x8000000000000000
+  #_ REGISTER_IN r5 -1
+  divdu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x8000000000000000
+  #_ REGISTER_OUT r5 -1

src/alloy/frontend/ppc/test/instr_divw.s

@@ -0,0 +1,109 @@
+test_divw_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divw_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divw_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divw_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divw_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divw_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divw_9:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divw_10:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divw_11:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divw r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+# TODO(benvanik): integer overflow (=0)
+#test_divw_12:
+#  #_ REGISTER_IN r4 0x80000000
+#  #_ REGISTER_IN r5 -1
+#  divw r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 0x80000000
+#  #_ REGISTER_OUT r5 -1

src/alloy/frontend/ppc/test/instr_divwu.s

@@ -0,0 +1,108 @@
+test_divwu_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+
+# TODO(benvanik): x64 ignore divide by zero (=0)
+#test_divwu_2:
+#  #_ REGISTER_IN r4 1
+#  #_ REGISTER_IN r5 0
+#  divwu r3, r4, r5
+#  blr
+#  #_ REGISTER_OUT r3 0
+#  #_ REGISTER_OUT r4 1
+#  #_ REGISTER_OUT r5 0
+
+test_divwu_3:
+  #_ REGISTER_IN r4 2
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 2
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r5 1
+
+test_divwu_4:
+  #_ REGISTER_IN r4 35
+  #_ REGISTER_IN r5 7
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 5
+  #_ REGISTER_OUT r4 35
+  #_ REGISTER_OUT r5 7
+
+test_divwu_5:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 1
+
+test_divwu_6:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_7:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_8:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_divwu_9:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 1
+
+test_divwu_10:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 1
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_11:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 0x000000007FFFFFFF
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 0x000000007FFFFFFF
+
+test_divwu_12:
+  #_ REGISTER_IN r4 0x80000000
+  #_ REGISTER_IN r5 -1
+  divwu r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0x80000000
+  #_ REGISTER_OUT r5 -1