diff --git a/src/xenia/cpu/frontend/ppc_hir_builder.cc b/src/xenia/cpu/frontend/ppc_hir_builder.cc
index b822baade..7a02ef3c4 100644
--- a/src/xenia/cpu/frontend/ppc_hir_builder.cc
+++ b/src/xenia/cpu/frontend/ppc_hir_builder.cc
@@ -123,13 +123,6 @@ bool PPCHIRBuilder::Emit(GuestFunction* function, uint32_t flags) {
     // Stash instruction offset. It's either the SOURCE_OFFSET or the COMMENT.
     instr_offset_list_[offset] = first_instr;
 
-    // Synchronize the PPC context as required.
-    // This will ensure all registers are saved to the PPC context before this
-    // instruction executes.
-    if (i.type->type & kXEPPCInstrTypeSynchronizeContext) {
-      ContextBarrier();
-    }
-
     if (!i.type) {
       XELOGE("Invalid instruction %.8llX %.8X", i.address, i.code);
       Comment("INVALID!");
@@ -138,6 +131,13 @@ bool PPCHIRBuilder::Emit(GuestFunction* function, uint32_t flags) {
     }
     ++i.type->translation_count;
 
+    // Synchronize the PPC context as required.
+    // This will ensure all registers are saved to the PPC context before this
+    // instruction executes.
+    if (i.type->type & kXEPPCInstrTypeSynchronizeContext) {
+      ContextBarrier();
+    }
+
     typedef int (*InstrEmitter)(PPCHIRBuilder& f, InstrData& i);
     InstrEmitter emit = (InstrEmitter)i.type->emit;