From 7ced7c932c074dadf0b15b61d89eacca90c2d08e Mon Sep 17 00:00:00 2001
From: Triang3l <triang3l@yandex.ru>
Date: Thu, 16 Aug 2018 14:02:53 +0300
Subject: [PATCH] [D3D12] Fix a typo in a blending register name

---
 src/xenia/gpu/d3d12/pipeline_cache.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/xenia/gpu/d3d12/pipeline_cache.cc b/src/xenia/gpu/d3d12/pipeline_cache.cc
index f10ae3d0e..cc74c7157 100644
--- a/src/xenia/gpu/d3d12/pipeline_cache.cc
+++ b/src/xenia/gpu/d3d12/pipeline_cache.cc
@@ -353,7 +353,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateBlendStateAndRenderTargets(
   regs.color_mask = color_mask;
   bool blend_enable =
       color_mask != 0 &&
-      !(register_file_->values[XE_GPU_REG_RB_COLOR_MASK].u32 & 0x20);
+      !(register_file_->values[XE_GPU_REG_RB_COLORCONTROL].u32 & 0x20);
   dirty |= regs.colorcontrol_blend_enable != blend_enable;
   regs.colorcontrol_blend_enable = blend_enable;
   static const Register kBlendControlRegs[] = {