From 76be00dfdf59b9333fd84529b875ebf6e79ee885 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Wed, 25 Dec 2013 21:58:40 -0800
Subject: [PATCH] Fiddling.

---
 src/alloy/backend/ivm/ivm_intcode.cc   | 6 ++++--
 src/alloy/frontend/ppc/ppc_emit_alu.cc | 2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/alloy/backend/ivm/ivm_intcode.cc b/src/alloy/backend/ivm/ivm_intcode.cc
index f2e828dac..27c0f4b4c 100644
--- a/src/alloy/backend/ivm/ivm_intcode.cc
+++ b/src/alloy/backend/ivm/ivm_intcode.cc
@@ -1112,7 +1112,7 @@ uint32_t IntCode_LOAD_CONTEXT_I32(IntCodeState& ics, const IntCode* i) {
 }
 uint32_t IntCode_LOAD_CONTEXT_I64(IntCodeState& ics, const IntCode* i) {
   ics.rf[i->dest_reg].i64 = *((int64_t*)(ics.context + ics.rf[i->src1_reg].u64));
-  DPRINT("%d (%.X) = ctx i64 +%d\n", ics.rf[i->dest_reg].i64, ics.rf[i->dest_reg].u64, ics.rf[i->src1_reg].u64);
+  DPRINT("%lld (%.llX) = ctx i64 +%d\n", ics.rf[i->dest_reg].i64, ics.rf[i->dest_reg].u64, ics.rf[i->src1_reg].u64);
   return IA_NEXT;
 }
 uint32_t IntCode_LOAD_CONTEXT_F32(IntCodeState& ics, const IntCode* i) {
@@ -1163,7 +1163,7 @@ uint32_t IntCode_STORE_CONTEXT_I32(IntCodeState& ics, const IntCode* i) {
 }
 uint32_t IntCode_STORE_CONTEXT_I64(IntCodeState& ics, const IntCode* i) {
   *((int64_t*)(ics.context + ics.rf[i->src1_reg].u64)) = ics.rf[i->src2_reg].i64;
-  DPRINT("ctx i64 +%d = %d (%.X)\n", ics.rf[i->src1_reg].u64, ics.rf[i->src2_reg].i64, ics.rf[i->src2_reg].u64);
+  DPRINT("ctx i64 +%d = %lld (%.llX)\n", ics.rf[i->src1_reg].u64, ics.rf[i->src2_reg].i64, ics.rf[i->src2_reg].u64);
   return IA_NEXT;
 }
 uint32_t IntCode_STORE_CONTEXT_F32(IntCodeState& ics, const IntCode* i) {
@@ -2792,10 +2792,12 @@ uint32_t IntCode_ROTATE_LEFT_I16(IntCodeState& ics, const IntCode* i) {
   return IA_NEXT;
 }
 uint32_t IntCode_ROTATE_LEFT_I32(IntCodeState& ics, const IntCode* i) {
+  // TODO(benvanik): use _rtol on vc++
   ics.rf[i->dest_reg].i32 = ROTL<uint32_t>(ics.rf[i->src1_reg].i32, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
 uint32_t IntCode_ROTATE_LEFT_I64(IntCodeState& ics, const IntCode* i) {
+  // TODO(benvanik): use _rtol64 on vc++
   ics.rf[i->dest_reg].i64 = ROTL<uint64_t>(ics.rf[i->src1_reg].i64, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc
index 5c0206f0e..fbaf2b79a 100644
--- a/src/alloy/frontend/ppc/ppc_emit_alu.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc
@@ -971,6 +971,8 @@ XEEMITTER(rlwinmx,      0x54000000, M  )(PPCFunctionBuilder& f, InstrData& i) {
   // m <- MASK(MB+32, ME+32)
   // RA <- r & m
   Value* v = f.Truncate(f.LoadGPR(i.M.RT), INT32_TYPE);
+  // TODO(benvanik): optimize srwi
+  // TODO(benvanik): optimize slwi
   // The compiler will generate a bunch of these for the special case of SH=0.
   // Which seems to just select some bits and set cr0 for use with a branch.
   // We can detect this and do less work.