diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.bin b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.bin
new file mode 100644
index 000000000..954231d04
Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.bin differ
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis
new file mode 100644
index 000000000..57e5c8c6a
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.dis
@@ -0,0 +1,41 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vrlimi128.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vrlimi128_1>:
+  100000:	18 80 1f 10 	vrlimi128 v4,v3,0,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vrlimi128_2>:
+  100008:	18 8f 1f 10 	vrlimi128 v4,v3,15,0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vrlimi128_3>:
+  100010:	1b 2f d7 55 	vrlimi128 v57,v58,15,0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vrlimi128_4>:
+  100018:	18 8f 1f 90 	vrlimi128 v4,v3,15,2
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vrlimi128_5>:
+  100020:	1a ef c7 d5 	vrlimi128 v55,v56,15,2
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vrlimi128_6>:
+  100028:	18 88 1f 10 	vrlimi128 v4,v3,8,0
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_vrlimi128_7>:
+  100030:	18 84 1f 10 	vrlimi128 v4,v3,4,0
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_vrlimi128_8>:
+  100038:	18 82 1f 10 	vrlimi128 v4,v3,2,0
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_vrlimi128_9>:
+  100040:	18 81 1f 10 	vrlimi128 v4,v3,1,0
+  100044:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.map b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.map
new file mode 100644
index 000000000..33c21f77c
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vrlimi128.map
@@ -0,0 +1,9 @@
+0000000000000000 t test_vrlimi128_1
+0000000000000008 t test_vrlimi128_2
+0000000000000010 t test_vrlimi128_3
+0000000000000018 t test_vrlimi128_4
+0000000000000020 t test_vrlimi128_5
+0000000000000028 t test_vrlimi128_6
+0000000000000030 t test_vrlimi128_7
+0000000000000038 t test_vrlimi128_8
+0000000000000040 t test_vrlimi128_9
diff --git a/src/alloy/frontend/ppc/test/instr_vrlimi128.s b/src/alloy/frontend/ppc/test/instr_vrlimi128.s
new file mode 100644
index 000000000..55a128d32
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_vrlimi128.s
@@ -0,0 +1,75 @@
+test_vrlimi128_1:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_2:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0xF, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_vrlimi128_3:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  # assember is busted here:
+  # vrlimi128 v4, v3, 0xF, 1
+  .long 0x188f1f50
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [04050607, 08090A0B, 0C0D0E0F, 00010203]
+
+test_vrlimi128_4:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0xF, 2
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [08090A0B, 0C0D0E0F, 00010203, 04050607]
+
+test_vrlimi128_5:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  # assember is busted here:
+  # vrlimi128 v4, v3, 0xF, 3
+  .long 0x188f1fd0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [0C0D0E0F, 00010203, 04050607, 08090A0B]
+
+test_vrlimi128_6:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x8, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_7:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x4, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, 04050607, CCCCCCCC, CCCCCCCC]
+
+test_vrlimi128_8:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x2, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, 08090A0B, CCCCCCCC]
+
+test_vrlimi128_9:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
+  vrlimi128 v4, v3, 0x1, 0
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, 0C0D0E0F]