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Randomly messing with address translation. Still not right.

This commit is contained in:
Ben Vanik 2013-10-22 21:05:56 -07:00
parent d4e19eb583
commit 62d4d5ce84
3 changed files with 29 additions and 21 deletions
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37
src/xenia/gpu/ring_buffer_worker.cc
View File

@ -148,9 +148,6 @@ void RingBufferWorker::ExecutePrimaryBuffer(
}
void RingBufferWorker::ExecuteIndirectBuffer(uint32_t ptr, uint32_t length) {
// Adjust pointer base.
ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (ptr & 0x1FFFFFFF);
XELOGGPU("[%.8X] ExecuteIndirectBuffer(%dw)", ptr, length);
// Execute commands!
@ -174,9 +171,6 @@ void RingBufferWorker::ExecuteIndirectBuffer(uint32_t ptr, uint32_t length) {
XEGETUINT32BE(packet_base + 1 * 4 + __m * 4)); \
}
#define TRANSLATE_ADDR(p) \
((p & ~0x3) + (primary_buffer_ptr_ & ~0x1FFFFFFF))
void RingBufferWorker::AdvancePtr(PacketArgs& args, uint32_t n) {
args.ptr = args.ptr + n * 4;
if (args.ptr_mask) {
@ -224,7 +218,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
args.ptr,
reg_data, target_index, reg_name ? reg_name : "");
ADVANCE_PTR(1);
WriteRegister(target_index, reg_data);
WriteRegister(packet_ptr, target_index, reg_data);
}
return 1 + count;
}
@ -249,8 +243,8 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
XELOGGPU("[%.8X] %.8X -> %.4X %s",
reg_ptr_2,
reg_data_2, reg_index_2, reg_name_2 ? reg_name_2 : "");
WriteRegister(reg_index_1, reg_data_1);
WriteRegister(reg_index_2, reg_data_2);
WriteRegister(packet_ptr, reg_index_1, reg_data_1);
WriteRegister(packet_ptr, reg_index_2, reg_data_2);
return 1 + 2;
}
break;
@ -307,7 +301,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
uint32_t list_length = READ_PTR();
XELOGGPU("[%.8X] Packet(%.8X): PM4_INDIRECT_BUFFER %.8X (%dw)",
packet_ptr, packet, list_ptr, list_length);
ExecuteIndirectBuffer(list_ptr, list_length);
ExecuteIndirectBuffer(GpuToCpu(list_ptr), list_length);
}
break;
@ -329,7 +323,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
// Memory.
XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3);
poll_reg_addr &= ~0x3;
value = XEGETUINT32LE(p + TRANSLATE_ADDR(poll_reg_addr));
value = XEGETUINT32LE(p + GpuToCpu(packet_ptr, poll_reg_addr));
value = GpuSwap(value, endianness);
} else {
// Register.
@ -399,7 +393,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
// & imm
value &= and_mask;
}
WriteRegister(rmw_info & 0x1FFF, value);
WriteRegister(packet_ptr, rmw_info & 0x1FFF, value);
}
break;
@ -418,9 +412,9 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
uint32_t value;
if (wait_info & 0x10) {
// Memory.
value = XEGETUINT32LE(p + TRANSLATE_ADDR(poll_reg_addr));
XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3);
poll_reg_addr &= ~0x3;
value = XEGETUINT32LE(p + GpuToCpu(packet_ptr, poll_reg_addr));
value = GpuSwap(value, endianness);
} else {
// Register.
@ -461,10 +455,11 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(write_reg_addr & 0x3);
write_reg_addr &= ~0x3;
write_data = GpuSwap(write_data, endianness);
XESETUINT32LE(p + TRANSLATE_ADDR(write_reg_addr), write_data);
XESETUINT32LE(p + GpuToCpu(packet_ptr, write_reg_addr),
write_data);
} else {
// Register.
WriteRegister(write_reg_addr, write_data);
WriteRegister(packet_ptr, write_reg_addr, write_data);
}
}
}
@ -496,7 +491,8 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
uint32_t address = READ_PTR();
uint32_t value = READ_PTR();
// Writeback initiator.
WriteRegister(XE_GPU_REG_VGT_EVENT_INITIATOR, initiator & 0x1F);
WriteRegister(packet_ptr, XE_GPU_REG_VGT_EVENT_INITIATOR,
initiator & 0x1F);
uint32_t data_value;
if ((initiator >> 31) & 0x1) {
// Write counter (GPU vblank counter?).
@ -508,7 +504,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(address & 0x3);
address &= ~0x3;
data_value = GpuSwap(data_value, endianness);
XESETUINT32LE(p + TRANSLATE_ADDR(address), data_value);
XESETUINT32LE(p + GpuToCpu(packet_ptr, address), data_value);
}
break;
@ -576,7 +572,7 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
XEASSERT(start == 0);
driver_->SetShader(
(XE_GPU_SHADER_TYPE)type,
TRANSLATE_ADDR(addr),
GpuToCpu(packet_ptr, addr),
start,
size * 4);
}
@ -667,7 +663,8 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
return 0;
}
void RingBufferWorker::WriteRegister(uint32_t index, uint32_t value) {
void RingBufferWorker::WriteRegister(
uint32_t packet_ptr, uint32_t index, uint32_t value) {
RegisterFile* regs = driver_->register_file();
XEASSERT(index < kXEGpuRegisterCount);
regs->values[index].u32 = value;
@ -680,7 +677,7 @@ void RingBufferWorker::WriteRegister(uint32_t index, uint32_t value) {
uint8_t* p = xe_memory_addr(memory_);
uint32_t scratch_addr = regs->values[XE_GPU_REG_SCRATCH_ADDR].u32;
uint32_t mem_addr = scratch_addr + (scratch_reg * 4);
XESETUINT32BE(p + TRANSLATE_ADDR(mem_addr), value);
XESETUINT32BE(p + GpuToCpu(primary_buffer_ptr_, mem_addr), value);
}
}
}

2
src/xenia/gpu/ring_buffer_worker.h
View File

@ -51,7 +51,7 @@ private:
void ExecutePrimaryBuffer(uint32_t start_index, uint32_t end_index);
void ExecuteIndirectBuffer(uint32_t ptr, uint32_t length);
uint32_t ExecutePacket(PacketArgs& args);
void WriteRegister(uint32_t index, uint32_t value);
void WriteRegister(uint32_t packet_ptr, uint32_t index, uint32_t value);
protected:
xe_memory_ref memory_;

11
src/xenia/gpu/xenos/xenos.h
View File

@ -65,6 +65,17 @@ XEFORCEINLINE uint32_t GpuSwap(uint32_t value, XE_GPU_ENDIAN endianness) {
}
}
XEFORCEINLINE uint32_t GpuToCpu(uint32_t p) {
return p;
}
XEFORCEINLINE uint32_t GpuToCpu(uint32_t base, uint32_t p) {
uint32_t upper = base & 0xFF000000;
uint32_t lower = p & 0x00FFFFFF;
return upper + lower;// -(((base >> 20) + 0x200) & 0x1000);
}
// XE_GPU_REG_SQ_PROGRAM_CNTL
typedef union {
XEPACKEDSTRUCTANONYMOUS({